| /linux/drivers/pci/controller/dwc/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 menu "DesignWare-based PCIe controllers"
39 required only for DT-based platforms. ACPI platforms with the
49 Versal2 SoCs. The AMD MDB Versal2 PCIe controller is based on
50 DesignWare IP and therefore the driver re-uses the DesignWare
60 SoCs. The PCI controller on Amlogic is based on DesignWare hardware
61 and therefore the driver re-uses the DesignWare core functions to
68 bool "Axis ARTPEC-6 PCIe controller (host mode)"
74 Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
75 host mode. This uses the DesignWare core.
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| /linux/drivers/firmware/arm_scmi/transports/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
14 This declares whether a shared memory based transport for SCMI is
20 This declares whether a message passing based transport for SCMI is
24 tristate "SCMI transport based on Mailbox"
30 Enable mailbox based transport for SCMI.
33 transport based on mailboxes, answer Y.
38 tristate "SCMI transport based on SMC"
44 Enable SMC based transport for SCMI.
47 transport based on SMC, answer Y.
52 bool "Enable atomic mode support for SCMI SMC transport"
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| /linux/Documentation/dev-tools/ |
| H A D | kasan.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 --------
11 designed to find out-of-bounds and use-after-free bugs.
16 2. Software Tag-Based KASAN
17 3. Hardware Tag-Based KASAN
19 Generic KASAN, enabled with CONFIG_KASAN_GENERIC, is the mode intended for
20 debugging, similar to userspace ASan. This mode is supported on many CPU
23 Software Tag-Based KASAN or SW_TAGS KASAN, enabled with CONFIG_KASAN_SW_TAGS,
25 This mode is only supported for arm64, but its moderate memory overhead allows
26 using it for testing on memory-restricted devices with real workloads.
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| /linux/Documentation/networking/devlink/ |
| H A D | devlink-eswitch-attr.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Devlink E-Switch Attribute
7 Devlink E-Switch supports two modes of operation: legacy and switchdev.
8 Legacy mode operates based on traditional MAC/VLAN steering rules. Switching
9 decisions are made based on MAC addresses, VLANs, etc. There is limited ability
12 On the other hand, switchdev mode allows for more advanced offloading
13 capabilities of the E-Switch to hardware. In switchdev mode, more switching
16 or scalable-functions (SFs) of the device. See more information about
20 In addition, the devlink E-Switch also comes with other attributes listed
26 The following is a list of E-Switch attributes.
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|
| /linux/Documentation/networking/device_drivers/ethernet/cirrus/ |
| H A D | cs89x0.rst | 1 .. SPDX-License-Identifier: GPL-2.0
33 2.1 CS8900-based Adapter Configuration
34 2.2 CS8920-based Adapter Configuration
40 4.2 Compiling the driver to support memory mode
46 5.2.1 Diagnostic Self-Test
66 The CS8900-based ISA Ethernet Adapters from Cirrus Logic follow
67 IEEE 802.3 standards and support half or full-duplex operation in ISA bus
69 in 16-bit ISA or EISA bus expansion slots and are available in
70 10BaseT-only or 3-media configurations (10BaseT, 10Base2, and AUI for 10Base-5
73 CS8920-based adapters are similar to the CS8900-based adapter with additional
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| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-class-net-qmi | 9 framing from '802.3' to 'raw-ip'.
12 mode. The netdev is an ordinary ethernet device in
13 '802.3' mode, and the driver expects to exchange
15 netdev is a headerless p-t-p device in 'raw-ip' mode,
22 link framing mode, changing this setting to 'Y' if the
23 firmware is configured for 'raw-ip' mode.
33 based network device, supported by recent Qualcomm based
50 created qmap mux based network device.
69 Set this to 'Y' to enable 'pass-through' mode, allowing packets
75 'Pass-through' mode can be enabled when the device is in
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|
| /linux/arch/arm/mach-lpc32xx/ |
| H A D | pm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-lpc32xx/pm.c
15 * direct-run, and halt modes. When switching between halt and run modes,
16 * the CPU transistions through direct-run mode. For Linux, direct-run
17 * mode is not used in normal operation. Halt mode is used when the
20 * Run mode:
23 * the HCLK_PLL rate. Linux runs in this mode.
25 * Direct-run mode:
27 * SYSCLK. SYSCLK is usually around 13MHz, but may vary based on SYSCLK
28 * source or the frequency of the main oscillator. In this mode, the
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| /linux/drivers/net/ethernet/intel/ice/ |
| H A D | ice_vlan_mode.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2019-2021, Intel Corporation. */
7 * ice_pkg_get_supported_vlan_mode - determine if DDP supports Double VLAN mode
26 return -ENOMEM; in ice_pkg_get_supported_vlan_mode()
29 sect->count = cpu_to_le16(1); in ice_pkg_get_supported_vlan_mode()
30 sect->offset = cpu_to_le16(ICE_META_VLAN_MODE_ENTRY); in ice_pkg_get_supported_vlan_mode()
42 arr[i] = le32_to_cpu(sect->entry.bm[i]); in ice_pkg_get_supported_vlan_mode()
56 * ice_aq_get_vlan_mode - get the VLAN mode of the device
58 * @get_params: structure FW fills in based on the current VLAN mode config
60 * Get VLAN Mode Parameters (0x020D)
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|
| /linux/Documentation/arch/x86/x86_64/ |
| H A D | fsgs.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 memory can use segment register based addressing mode. The following
10 Segment-register:Byte-address
12 The segment base address is added to the Byte-address to compute the
14 instances of data with the identical Byte-address, i.e. the same code. The
15 selection of a particular instance is purely based on the base-address in
18 In 32-bit mode the CPU provides 6 segments, which also support segment
21 In 64-bit mode the CS/SS/DS/ES segments are ignored and the base address is
23 still functional in 64-bit mode.
26 ------------------------------
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|
| /linux/lib/ |
| H A D | Kconfig.kasan | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # This config refers to the generic KASAN mode.
32 compile-time constants for better performance.
35 def_bool $(cc-option, -fsanitize=kernel-address)
38 def_bool $(cc-option, -fsanitize=kernel-hwaddress)
55 Enables KASAN (Kernel Address Sanitizer) - a dynamic memory safety
56 error detector designed to find out-of-bounds and use-after-free bugs.
58 See Documentation/dev-tools/kasan.rst for details.
65 …def_bool (CC_IS_CLANG && $(cc-option,-fsanitize=kernel-address -mllvm -asan-kernel-mem-intrinsic-p…
66 (CC_IS_GCC && $(cc-option,-fsanitize=kernel-address --param asan-kernel-mem-intrinsic-prefix=1))
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|
| /linux/tools/perf/pmu-events/arch/x86/jaketown/ |
| H A D | uncore-memory.json | 12 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
30 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
57 …ption": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
66 …tion": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
79 "PublicDescription": "Uncore Fixed Counter - uclks",
117 …iMC can correct up to 4 bit errors in independent channel mode and 8 bit errors in lockstep mode.",
121 "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
126 …ent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, a…
131 "BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
136 …ent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, a…
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|
| /linux/Documentation/admin-guide/mm/ |
| H A D | numa_memory_policy.rst | 10 supported platforms with Non-Uniform Memory Access architectures since 2.4.?.
16 (``Documentation/admin-guide/cgroup-v1/cpusets.rst``)
19 programming interface that a NUMA-aware application can take advantage of. When
28 ------------------------
41 not to overload the initial boot node with boot-time
45 this is an optional, per-task policy. When defined for a
61 In a multi-threaded task, task policies apply only to the thread
69 changes its task policy remain where they were allocated based on
98 mapping-- i.e., at Copy-On-Write.
101 virtual address space--a.k.a. threads--independent of when
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|
| /linux/drivers/net/can/sja1000/ |
| H A D | plx_pci.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2008-2010 Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>
7 * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
8 * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
26 MODULE_DESCRIPTION("Socket-CAN driver for PLX90xx PCI-bridge cards with "
37 /* Pointer to device-dependent reset function */
71 * This means normal output mode, push-pull and the correct polarity.
86 /* SJA1000 Control Register in the BasicCAN Mode */
89 /* States of some SJA1000 registers after hardware reset in the BasicCAN mode*/
95 /* States of some SJA1000 registers after hardware reset in the PeliCAN mode*/
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|
| /linux/Documentation/devicetree/bindings/ |
| H A D | common-properties.txt | 5 ----------
13 - big-endian: Boolean; force big endian register accesses
15 know the peripheral always needs to be accessed in big endian (BE) mode.
16 - little-endian: Boolean; force little endian register accesses
18 peripheral always needs to be accessed in little endian (LE) mode.
19 - native-endian: Boolean; always use register accesses matched to the
20 endianness of the kernel binary (e.g. LE vmlinux -> readl/writel,
21 BE vmlinux -> ioread32be/iowrite32be). In this case no byte swaps
22 will ever be performed. Use this if the hardware "self-adjusts"
23 register endianness based on the CPU's configured endianness.
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|
| /linux/Documentation/devicetree/bindings/net/ |
| H A D | qcom,qca807x.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christian Marangi <ansuelsmth@gmail.com>
11 - Robert Marko <robert.marko@sartura.hr>
15 IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and
16 1000BASE-T PHY-s.
21 Both models have a combo port that supports 1000BASE-X and
22 100BASE-FX fiber.
25 output only pins that natively drive LED-s for up to 2 attached
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|
| /linux/net/dsa/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
22 tristate "No-op tag driver"
28 tristate "Tag driver for Atheros AR9331 SoC with built-in switch"
31 the Atheros AR9331 SoC with built-in switch.
38 tristate "Tag driver for Broadcom switches using in-frame headers"
45 tristate "Tag driver for BCM63xx legacy switches using in-frame headers"
55 tristate "Tag driver for BCM53xx legacy switches using in-frame headers"
118 (VSC7511, VSC7512, VSC7513, VSC7514, VSC9953, VSC9959). In this mode,
120 hardware-defined injection/extraction frame header. Flow control
122 this mode.
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|
| /linux/Documentation/input/devices/ |
| H A D | edt-ft5x06.rst | 1 EDT ft5x06 based Polytouch devices
2 ----------------------------------
4 The edt-ft5x06 driver is useful for the EDT "Polytouch" family of capacitive
5 touch screens. Note that it is *not* suitable for other devices based on the
6 focaltec ft5x06 devices, since they contain vendor-specific firmware. In
18 allows setting the "click"-threshold in the range from 0 to 80.
34 /sys/kernel/debug/i2c/<i2c-bus>/<i2c-device>/
39 $ ls -l /sys/bus/i2c/drivers/edt_ft5x06
44 0-0038 -> ../../../../devices/platform/soc/fcfee800.i2c/i2c-0/0-0038
48 /sys/kernel/debug/i2c/i2c-0/0-0038/
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|
| /linux/drivers/ata/ |
| H A D | pata_cs5535.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata-cs5535.c - CS5535 PATA for new ATA layer
4 * (C) 2005-2006 Red Hat Inc
7 * based upon cs5535.c from AMD <Jens.Altmann@amd.com> as cleaned up and
9 * and Alexander Kiausch <alex.kiausch@t-online.de>
11 * Loosely based on the piix & svwks drivers.
32 * The Geode (Aka Athlon GX now) uses an internal MSR based
58 * cs5535_cable_detect - detect cable type
68 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in cs5535_cable_detect()
78 * cs5535_set_piomode - PIO setup
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|
| /linux/drivers/hid/intel-thc-hid/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
13 is comprised of 3 key functional blocks: A natively half-duplex
21 tristate "Intel QuickSPI driver based on Intel Touch Host Controller"
24 Intel QuickSPI, based on Touch Host Controller (THC), implements
26 mode, and controls THC hardware sequencer to accelerate HIDSPI
32 tristate "Intel QuickI2C driver based on Intel Touch Host Controller"
37 mode, and controls THC hardware sequencer to accelerate HIDI2C
|
| /linux/Documentation/devicetree/bindings/mailbox/ |
| H A D | cix,sky1-mbox.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/cix,sky1-mbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Guomin Chen <Guomin.Chen@cixtech.com>
19 typically used in pairs-one for receiving and one for transmitting.
22 channel 0-7 - Fast channel with 32bit transmit register and IRQ support
23 channel 8 - Doorbell mode,using the mailbox as an interrupt-generating
25 channel 9 - Fifo based channel with 32*32bit depth fifo and IRQ support
26 channel 10 - Reg based channel with 32*32bit transmit register and
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|
| /linux/Documentation/networking/device_drivers/ethernet/intel/ |
| H A D | ice.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 2018-2021 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Important Notes
16 - Additional Features & Configurations
17 - Performance Optimization
28 This driver supports XDP (Express Data Path) and AF_XDP zero-copy. Note that
43 -------------------------------------------
44 Devices based on the Intel(R) Ethernet Controller 800 Series are designed to
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|
| H A D | e1000e.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 2008-2018 Intel Corporation.
13 - Identifying Your Adapter
14 - Command Line Parameters
15 - Additional Configurations
16 - Support
48 ---------------------
49 :Valid Range: 0,1,3,4,100-100000
69 it dynamically adjusts the InterruptThrottleRate value based on the traffic
82 - 0: Off
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|
| /linux/Documentation/driver-api/backlight/ |
| H A D | lp855x-driver.rst | 15 -----------
26 Backlight control mode.
28 Value: pwm based or register based
37 ------------------------
49 Only valid when brightness is pwm input mode.
58 1) lp8552 platform data: i2c register mode with new eeprom data::
68 .name = "lcd-bl",
75 2) lp8556 platform data: pwm input mode with default rom data::
|
| /linux/mm/kasan/ |
| H A D | hw_tags.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains core hardware tag-based KASAN code.
49 * Whether the selected mode is synchronous, asynchronous, or asymmetric.
88 return -EINVAL; in early_kasan_flag()
95 return -EINVAL; in early_kasan_flag()
101 /* kasan.mode=sync/async/asymm */
105 return -EINVAL; in early_kasan_mode()
114 return -EINVAL; in early_kasan_mode()
118 early_param("kasan.mode", early_kasan_mode);
124 return -EINVAL; in early_kasan_flag_vmalloc()
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|
| /linux/Documentation/devicetree/bindings/spi/ |
| H A D | brcm,bcm63xx-hsspi.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,bcm63xx-hsspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - William Zhang <william.zhang@broadcom.com>
11 - Kursad Oney <kursad.oney@broadcom.com>
12 - Jonas Gorski <jonas.gorski@gmail.com>
16 early MIPS based chips such as BCM6328 and BCM63268. This initial rev 1.0
17 controller was carried over to recent ARM based chips, such as BCM63138,
18 BCM4908 and BCM6858. The old MIPS based chip should continue to use the
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|