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/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dcdns,sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
15 - enum:
16 - amd,pensando-elba-sd4hc
17 - microchip,mpfs-sd4hc
18 - socionext,uniphier-sd4hc
19 - const: cdns,sd4hc
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H A Dmmc-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schema
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H A Dbrcm,sdhci-brcmstb.txt3 This file documents differences between the core properties in mmc.txt
4 and the properties used by the sdhci-brcmstb driver.
11 - compatible: should be one of the following
12 - "brcm,bcm7425-sdhci"
13 - "brcm,bcm7445-sdhci"
14 - "brcm,bcm7216-sdhci"
16 Refer to clocks/clock-bindings.txt for generic clock consumer properties.
21 sd-uhs-sdr50;
22 sd-uhs-ddr50;
23 sd-uhs-sdr104;
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H A Dbrcm,sdhci-brcmstb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/brcm,sdhci-brcmstb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Al Cooper <alcooperx@gmail.com>
11 - Florian Fainelli <f.fainelli@gmail.com>
16 - items:
17 - enum:
18 - brcm,bcm7216-sdhci
19 - const: brcm,bcm7445-sdhci
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H A Dsprd,sdhci-r11.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/sprd,sdhci-r11.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
16 const: sprd,sdhci-r11
19 maxItems: 1
22 maxItems: 1
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H A Dhi3798cv200-dw-mshc.txt4 Read synopsys-dw-mshc.txt for more details
7 a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
9 by synopsys-dw-mshc.txt and the properties used by the Hisilicon Hi3798CV200
13 - compatible: Should contain "hisilicon,hi3798cv200-dw-mshc".
14 - clocks: A list of phandle + clock-specifier pairs for the clocks listed
15 in clock-names.
16 - clock-names: Should contain the following:
17 "ciu" - The ciu clock described in synopsys-dw-mshc.txt.
18 "biu" - The biu clock described in synopsys-dw-mshc.txt.
19 "ciu-sample" - Hi3798CV200 extended phase clock for ciu sampling.
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H A Dhisilicon,hi3798cv200-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/hisilicon,hi3798cv200-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yang Xiwen <forbidden405@outlook.com>
15 - hisilicon,hi3798cv200-dw-mshc
16 - hisilicon,hi3798mv200-dw-mshc
19 maxItems: 1
22 maxItems: 1
26 - description: bus interface unit clock
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/freebsd/sys/dev/mmc/
H A Dmmc_helpers.c9 * 1. Redistributions of source code must retain the above copyright
34 #include <dev/mmc/bridge.h>
35 #include <dev/mmc/mmc_helpers.h>
44 * All UHS-I modes requires 1.8V signaling. in mmc_parse_sd_speed()
46 if (device_has_property(dev, "no-1-8-v")) in mmc_parse_sd_speed()
48 if (device_has_property(dev, "cap-sd-highspeed")) in mmc_parse_sd_speed()
49 host->caps |= MMC_CAP_HSPEED; in mmc_parse_sd_speed()
50 if (device_has_property(dev, "sd-uhs-sdr12") && !no_18v) in mmc_parse_sd_speed()
51 host->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_SIGNALING_180; in mmc_parse_sd_speed()
52 if (device_has_property(dev, "sd-uhs-sdr25") && !no_18v) in mmc_parse_sd_speed()
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/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos5260-xyref5260.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
27 stdout-path = "serial2:115200n8";
31 compatible = "fixed-clock";
32 clock-frequency = <24000000>;
33 clock-output-names = "fin_pll";
34 #clock-cells = <0>;
37 ioclk_pcm: clock-pcm-ext {
38 compatible = "fixed-clock";
39 clock-frequency = <2048000>;
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dipq9574-al02-c7.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * IPQ9574 AL02-C7 board device tree source
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
9 /dts-v1/;
14 model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
15 compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
22 stdout-path = "serial0:115200n8";
27 pinctrl-0 = <&uart2_pins>;
28 pinctrl-names = "default";
33 pinctrl-0 = <&sdc_default_state>;
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H A Dipq9574-rdp433.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
9 /dts-v1/;
11 #include "ipq9574-rdp-common.dtsi"
14 model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL0
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H A Dipq9574-rdp418.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
6 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
9 /dts-v1/;
11 #include "ipq9574-rdp-commo
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H A Dipq5332-mi01.2.dts1 // SPDX-License-Identifier: BSD-3-Clause
3 * IPQ5332 AP-MI01.2 board device tree source
5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
8 /dts-v1/;
14 compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332";
21 stdout-path = "serial0";
26 pinctrl-0 = <&serial_0_pins>;
27 pinctrl-names = "default";
32 clock-frequency = <400000>;
33 pinctrl-0 = <&i2c_1_pins>;
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H A Dipq5332-rdp441.dts1 // SPDX-License-Identifier: BSD-3-Clause
3 * IPQ5332 AP-MI01.2 board device tree source
5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
8 /dts-v1/;
10 #include "ipq5332-rdp-common.dtsi"
14 compatible = "qcom,ipq5332-a
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H A Dipq5332-rdp468.dts1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
8 /dts-v1/;
10 #include "ipq5332-rdp-common.dtsi"
14 compatible = "qcom,ipq5332-ap-mi0
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H A Dipq5332-rdp474.dts1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
8 /dts-v1/;
10 #include "ipq5332-rdp-common.dtsi"
14 compatible = "qcom,ipq5332-ap-mi0
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H A Dipq5332-rdp442.dts1 // SPDX-License-Identifier: BSD-3-Clause
8 /dts-v1/;
10 #include "ipq5332-rdp-common.dtsi"
14 compatible = "qcom,ipq5332-ap-mi01.3", "qcom,ipq5332";
18 clock-frequenc
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/freebsd/sys/contrib/device-tree/src/arm/rockchip/
H A Drk3288-tinker-s.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "rk3288-tinker.dtsi"
12 compatible = "asus,rk3288-tinker-s", "rockchip,rk3288";
16 bus-width = <8>;
17 cap-mmc-highspeed;
18 non-removable;
19 pinctrl-names = "default";
20 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
21 max-frequency = <150000000>;
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/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3328-nanopi-r2c-plus.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
9 /dts-v1/;
10 #include "rk3328-nanopi-r2c.dts"
14 compatible = "friendlyarm,nanopi-r2c-plus", "rockchip,rk3328";
22 bus-width = <8>;
23 cap-mmc-highspeed;
24 max-frequency = <150000000>;
25 mmc-ddr-1_8v;
26 mmc-hs200-1_8v;
27 non-removable;
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/freebsd/sys/contrib/device-tree/src/riscv/microchip/
H A Dmpfs-polarberry.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2022 Microchip Technology Inc */
4 /dts-v1/;
7 #include "mpfs-polarberry-fabric.dtsi"
19 stdout-path = "serial0:115200n8";
38 phy-mode = "sgmii";
39 phy-handl
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H A Dmpfs-sev-kit.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
7 #include "mpfs-sev-kit-fabric.dtsi"
10 #address-cells = <2>;
11 #size-cells = <2>;
12 model = "Microchip PolarFire-So
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H A Dmicrochip-mpfs-icicle-kit.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
6 #include "microchip-mpfs.dtsi"
12 model = "Microchip PolarFire-SoC Icicle Kit";
13 compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
25 stdout-path = "serial1:115200n8";
29 timebase-frequency = <RTCCLK_FREQ>;
48 clock-frequency = <125000000>;
67 &mmc {
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/freebsd/sys/contrib/device-tree/src/arm64/allwinner/
H A Dsun50i-h618-longan-module-3h.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "sun50i-h616.dtsi"
7 #include "sun50i-h616-cpu-opp.dtsi"
10 cpu-supply = <&reg_dcdc2>;
14 pinctrl-names = "default";
15 pinctrl-0 = <&mmc2_pins>;
16 vmmc-supply = <&reg_dldo1>;
17 vqmmc-supply = <&reg_aldo1>;
18 bus-width = <8>;
19 non-removable;
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/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynos7885-jackpotlte.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Galaxy A8 2018 (jackpotlte/SM-A530F) device tree source
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
18 chassis-type = "handset";
28 stdout-path = &serial_2;
38 gpio-keys {
39 compatible = "gpio-keys";
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/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-gxl-s905x-hwacom-amazetv.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxl-s905x.dtsi"
13 compatible = "hwacom,amazetv", "amlogic,s905x", "amlogic,meson-gxl";
22 stdout-path = "serial0:115200n8";
30 vddio_card: gpio-regulator {
31 compatible = "regulator-gpio";
33 regulator-name = "VDDIO_CARD";
34 regulator-min-microvolt = <1800000>;
35 regulator-max-microvolt = <3300000>;
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