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/freebsd/usr.bin/systat/
H A Dzarc.c52 struct zfield misses; member
88 "Rate", "Hits", "Misses", "Rate", "Hits", "Misses"); in labelzarc()
103 calc_rate(uint64_t hits, uint64_t misses) in calc_rate() argument
106 return 100 * hits / (hits + misses); in calc_rate()
116 delta->misses.stat = (curstat.misses.stat - oldstat.misses.stat); \ in domode()
117 rate->current.stat = calc_rate(delta->hits.stat, delta->misses.stat); \ in domode()
118 rate->total.stat = calc_rate(curstat.hits.stat, curstat.misses.stat) in domode()
151 #define MISSES(stat) DO(delta.misses.stat, 31+1+5+7, 6); \ in showzarc() macro
152 DO(curstat.misses.stat, 31+1+5+7+7+8+5+7, 6) in showzarc()
153 #define E(stat) RATES(stat); HITS(stat); MISSES(stat); ++row in showzarc()
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen1/
H A Drecommended.json24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
41 "BriefDescription": "All L2 Cache Misses",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
59 "BriefDescription": "L2 Cache Misses from L2 HWPF",
72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
78 "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses",
97 "BriefDescription": "L3 Misses (includes Chg2X)",
117 "BriefDescription": "L1 ITLB Misses",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen2/
H A Drecommended.json24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
41 "BriefDescription": "All L2 Cache Misses",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
59 "BriefDescription": "L2 Cache Misses from L2 HWPF",
72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
78 "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses",
97 "BriefDescription": "L3 Misses (includes Chg2X)",
117 "BriefDescription": "L1 ITLB Misses",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen3/
H A Drecommended.json24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
41 "BriefDescription": "All L2 Cache Misses",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
59 "BriefDescription": "L2 Cache Misses from L2 Cache HWPF",
72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
78 "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses",
97 "BriefDescription": "L3 Misses (includes cacheline state change requests)",
153 "BriefDescription": "L1 ITLB Misses",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/haswell/
H A Dvirtual-memory.json3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
8 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.",
13 …"BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translati…
18 …"PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translat…
33 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)",
43 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)",
58 …"PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.",
77 …"PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks …
87 …"PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in …
97 …unts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
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/freebsd/lib/libpmc/pmu-events/arch/x86/haswellx/
H A Dvirtual-memory.json3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
8 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.",
13 …"BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translati…
18 …"PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translat…
33 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)",
43 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)",
58 …"PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.",
77 …"PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks …
87 …"PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in …
97 …unts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
[all …]
H A Duncore-cache.json10 … "BriefDescription": "All LLC Misses (code+ data rd + data wr - including demand and prefetch)",
31 …"BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derive…
42 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.mi…
75 … "BriefDescription": "LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode",
86 …"BriefDescription": "LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcod…
97 …"BriefDescription": "LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcod…
108 …"BriefDescription": "LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode",
119 …"BriefDescription": "ItoM write misses (as part of fast string memcpy stores) + PCIe full line wri…
130 …"BriefDescription": "PCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opco…
/freebsd/lib/libpmc/pmu-events/arch/x86/broadwellde/
H A Dvirtual-memory.json3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
9 …"PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of an…
23 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).",
32 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).",
57 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
68 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
79 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
95 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
101 …"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of a…
115 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).",
[all …]
H A Duncore-cache.json10 … "BriefDescription": "All LLC Misses (code+ data rd + data wr - including demand and prefetch)",
31 …"BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derive…
42 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.mi…
75 … "BriefDescription": "LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode",
86 …"BriefDescription": "LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcod…
97 …"BriefDescription": "LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcod…
108 …"BriefDescription": "LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode",
119 …"BriefDescription": "ItoM write misses (as part of fast string memcpy stores) + PCIe full line wri…
130 …"BriefDescription": "PCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opco…
/freebsd/lib/libpmc/pmu-events/arch/x86/broadwell/
H A Dvirtual-memory.json3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
9 …"PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of an…
23 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).",
32 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).",
57 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
68 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
79 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
95 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
101 …"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of a…
115 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/broadwellx/
H A Dvirtual-memory.json3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
9 …"PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of an…
23 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).",
32 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).",
57 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
68 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
79 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
95 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
101 …"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of a…
115 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).",
[all …]
H A Duncore-cache.json10 … "BriefDescription": "All LLC Misses (code+ data rd + data wr - including demand and prefetch)",
31 …"BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derive…
42 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.mi…
75 … "BriefDescription": "LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode",
86 …"BriefDescription": "LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcod…
97 …"BriefDescription": "LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcod…
108 …"BriefDescription": "LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode",
119 …"BriefDescription": "ItoM write misses (as part of fast string memcpy stores) + PCIe full line wri…
130 …"BriefDescription": "PCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opco…
/freebsd/lib/libpmc/pmu-events/arch/x86/ivytown/
H A Duncore-cache.json10 … "BriefDescription": "All LLC Misses (code+ data rd + data wr - including demand and prefetch)",
31 …"BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derive…
42 …"BriefDescription": "LLC misses - Uncacheable reads. Derived from unc_c_tor_inserts.miss_opcode.un…
53 …"BriefDescription": "LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode.rfo_p…
64 …"BriefDescription": "LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcod…
75 …"BriefDescription": "LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcod…
86 …"BriefDescription": "PCIe allocating writes that miss LLC - DDIO misses. Derived from unc_c_tor_in…
97 …"BriefDescription": "LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode.…
108 …"BriefDescription": "LLC misses for ItoM writes (as part of fast string memcpy stores). Derived fr…
119 …"BriefDescription": "LLC misses for PCIe non-snoop reads. Derived from unc_c_tor_inserts.miss_opco…
[all …]
H A Dvirtual-memory.json35 …"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand…
55 …"PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by dema…
70 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
90 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
129 "BriefDescription": "Completed page walks in ITLB due to STLB load misses for large pages",
134 … "PublicDescription": "Completed page walks in ITLB due to STLB load misses for large pages.",
139 "BriefDescription": "Misses at all ITLB levels that cause page walks",
144 "PublicDescription": "Misses in all ITLB levels that cause page walks.",
159 "BriefDescription": "Misses in all ITLB levels that cause completed page walks",
164 "PublicDescription": "Misses in all ITLB levels that cause completed page walks.",
/freebsd/lib/libpmc/pmu-events/arch/x86/tremontx/
H A Dvirtual-memory.json14 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to load…
25 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page…
36 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G pag…
48 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or …
60 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag…
96 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to stor…
107 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to any pag…
118 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G pa…
130 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 2M or…
142 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 4K pa…
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/ivybridge/
H A Dvirtual-memory.json17 …"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand…
37 …"PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by dema…
52 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
72 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
111 "BriefDescription": "Completed page walks in ITLB due to STLB load misses for large pages",
116 … "PublicDescription": "Completed page walks in ITLB due to STLB load misses for large pages.",
121 "BriefDescription": "Misses at all ITLB levels that cause page walks",
126 "PublicDescription": "Misses in all ITLB levels that cause page walks.",
141 "BriefDescription": "Misses in all ITLB levels that cause completed page walks",
146 "PublicDescription": "Misses in all ITLB levels that cause completed page walks.",
/freebsd/lib/libpmc/pmu-events/arch/x86/elkhartlake/
H A Dvirtual-memory.json14 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to load…
25 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page…
36 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or …
48 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag…
84 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 2M or…
96 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 4K pa…
132 "BriefDescription": "Counts the number of Extended Page Directory Entry misses.",
139 …"PublicDescription": "Counts the number Extended Page Directory Entry misses. The Extended Page D…
156 "BriefDescription": "Counts the number of Extended Page Directory Pointer Entry misses.",
163 …"PublicDescription": "Counts the number Extended Page Directory Pointer Entry misses. The Extende…
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/jaketown/
H A Dvirtual-memory.json3 "BriefDescription": "Load misses in all DTLB levels that cause page walks.",
22 "BriefDescription": "Load misses at all DTLB levels that cause completed page walks.",
36 …unts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
41 "BriefDescription": "Store misses in all DTLB levels that cause page walks.",
59 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
95 "BriefDescription": "Misses at all ITLB levels that cause page walks.",
113 "BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
127 …is event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.",
/freebsd/lib/libpmc/pmu-events/arch/x86/sandybridge/
H A Dvirtual-memory.json3 "BriefDescription": "Load misses in all DTLB levels that cause page walks.",
22 "BriefDescription": "Load misses at all DTLB levels that cause completed page walks.",
36 …unts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
41 "BriefDescription": "Store misses in all DTLB levels that cause page walks.",
59 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
95 "BriefDescription": "Misses at all ITLB levels that cause page walks.",
113 "BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
127 …is event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.",
/freebsd/lib/libpmc/pmu-events/arch/x86/bonnell/
H A Dvirtual-memory.json11 "BriefDescription": "DTLB misses due to load operations.",
19 "BriefDescription": "DTLB misses due to store operations.",
27 "BriefDescription": "L0 DTLB misses due to load operations.",
35 "BriefDescription": "L0 DTLB misses due to store operations",
59 "BriefDescription": "ITLB misses.",
62 "EventName": "ITLB.MISSES",
/freebsd/lib/libpmc/
H A Dpmc.corei7.3190 Counts all load misses that cause a page walk
199 Number of DTLB cache load misses where the low part of the linear to
224 Counts both primary and secondary misses to the TLB
378 L2 loads include both L1D demand misses as well as L1D prefetches.
384 L2 loads include both L1D demand misses as well as L1D prefetches.
388 L2 loads include both L1D demand misses as well as L1D prefetches.
392 L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.
398 L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.
402 L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.
406 L2 instruction fetches include both L1I demand misses as well as L1I instruction
[all …]
H A Dpmc.westmere.3198 Counts all load misses that cause a page walk
210 Number of DTLB cache load misses where the low part of the linear to
232 Counts both primary and secondary misses to the TLB
377 L2 loads include both L1D demand misses as well as L1D prefetches.
383 L2 loads include both L1D demand misses as well as L1D prefetches.
387 L2 loads include both L1D demand misses as well as L1D prefetches.
391 L2 RFO requests include both L1D demand RFO misses as well as L1D RFO
398 L2 RFO requests include both L1D demand RFO misses as well as L1D RFO
404 RFO misses as well as L1D RFO prefetches.
408 L2 instruction fetches include both L1I demand misses as well as L1I
[all …]
H A Dpmc.haswellxeon.3221 Misses in all TLB levels that cause a page walk of any
225 Completed page walks due to demand load misses
229 Completed page walks due to demand load misses
234 due to demand load misses
240 Load misses that missed DTLB but hit STLB (4K).
243 Load misses that missed DTLB but hit STLB (2M).
250 DTLB demand load misses with low part of linear-to-
354 Increments the number of outstanding L1D misses
363 Completed page walks due to store misses in one or
367 Completed page walks due to store misses in one or
[all …]
H A Dpmc.haswell.3220 Misses in all TLB levels that cause a page walk of any
224 Completed page walks due to demand load misses
228 Completed page walks due to demand load misses
233 due to demand load misses
239 Load misses that missed DTLB but hit STLB (4K).
242 Load misses that missed DTLB but hit STLB (2M).
249 DTLB demand load misses with low part of linear-to-
351 Increments the number of outstanding L1D misses every cycle.
359 Completed page walks due to store misses in one or
363 Completed page walks due to store misses in one or
[all …]
/freebsd/sys/contrib/openzfs/man/man1/
H A Darcstat.188 Demand misses per second
94 Demand data misses per second
100 Demand metadata misses per second
116 ARC misses per second
118 Metadata misses per second
126 Prefetch misses per second
132 Prefetch data misses per second
138 Prefetch metadata misses per second
173 L2ARC misses per second

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