Lines Matching full:misses

198 Counts all load misses that cause a page walk
210 Number of DTLB cache load misses where the low part of the linear to
232 Counts both primary and secondary misses to the TLB
377 L2 loads include both L1D demand misses as well as L1D prefetches.
383 L2 loads include both L1D demand misses as well as L1D prefetches.
387 L2 loads include both L1D demand misses as well as L1D prefetches.
391 L2 RFO requests include both L1D demand RFO misses as well as L1D RFO
398 L2 RFO requests include both L1D demand RFO misses as well as L1D RFO
404 RFO misses as well as L1D RFO prefetches.
408 L2 instruction fetches include both L1I demand misses as well as L1I
413 L2 instruction fetches include both L1I demand misses as well as L1I
419 demand misses as well as L1I instruction prefetches.
425 Counts L2 prefetch misses for both code and data.
431 Counts all L2 misses for both code and data.
439 L2 demand loads are both L1D demand misses and L1D prefetches.
444 L2 demand loads are both L1D demand misses and L1D
450 L2 demand loads are both L1D demand misses and
456 L2 demand loads are both L1D demand misses and
462 misses and L1D prefetches.
569 Counts uncore Last Level Cache misses.
587 Counts the number of misses in the STLB which causes a page walk.
590 Counts number of misses in the STLB which resulted in a completed page walk.
593 Counts cycles of page walk due to misses in the STLB.
596 Counts the number of DTLB first level misses that hit in the second level
601 Counts number of completed large page walks due to misses in the STLB.
699 .It Li L1I.MISSES
703 instruction cache misses, streaming buffer misses, victim cache misses and
720 Counts the number of misses in all levels of the ITLB which causes a page
724 Counts number of misses in all levels of the ITLB which resulted in a
731 Counts number of completed large page walks due to misses in the STLB.
837 misses, etc.
1130 This is counting secondary L1D misses.
1137 Counts both primary and secondary misses to the TLB.