| /linux/Documentation/devicetree/bindings/display/mediatek/ |
| H A D | mediatek,merge.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,merge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek display merge
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
14 Mediatek display merge, namely MERGE, is used to merge two slice-per-line
15 inputs into one side-by-side output.
16 MERGE device node must be siblings to the central MMSYS_CONFIG node.
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| /linux/drivers/gpu/drm/nouveau/nvkm/engine/ce/ |
| H A D | gt215.c | 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
30 #include <engine/fifo.h>
45 struct nvkm_subdev *subdev = &ce->engine.subdev; in gt215_ce_intr()
46 struct nvkm_device *device = subdev->device; in gt215_ce_intr()
47 const u32 base = subdev->inst * 0x1000; in gt215_ce_intr()
53 const struct nvkm_enum *en = in gt215_ce_intr() local
58 en ? en->name : "", chan ? chan->id : -1, in gt215_ce_intr()
59 chan ? chan->inst->addr : 0, in gt215_ce_intr()
60 chan ? chan->name : "unknown", in gt215_ce_intr()
72 { -1, -1, GT212_DMA },
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| /linux/drivers/gpu/drm/nouveau/nvkm/engine/sec/ |
| H A D | g98.c | 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
25 #include <engine/fifo.h>
45 struct nvkm_subdev *subdev = &sec->engine.subdev; in g98_sec_intr()
46 struct nvkm_device *device = subdev->device; in g98_sec_intr()
52 const struct nvkm_enum *en = in g98_sec_intr() local
57 en ? en->name : "UNKNOWN", chan ? chan->id : -1, in g98_sec_intr()
58 chan ? chan->inst->addr : 0, in g98_sec_intr()
59 chan ? chan->name : "unknown", in g98_sec_intr()
71 { -1, -1, G98_SEC },
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| H A D | nv50.c | 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
29 #include <engine/fifo.h>
35 return fb->func->ram_new(&fb->base, pram); in nv50_fb_ram_new()
138 struct nvkm_subdev *subdev = &fb->base.subdev; in nv50_fb_intr()
139 struct nvkm_device *device = subdev->device; in nv50_fb_intr()
141 const struct nvkm_enum *en, *re, *cl, *sc; in nv50_fb_intr() local
159 if (device->chipset < 0xa3 || in nv50_fb_intr()
160 device->chipset == 0xaa || device->chipset == 0xac) { in nv50_fb_intr()
173 en = nvkm_enum_find(vm_engine, st0); in nv50_fb_intr()
176 if (cl && cl->data) sc = nvkm_enum_find(cl->data, st3); in nv50_fb_intr()
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| /linux/Documentation/translations/sp_SP/process/ |
| H A D | maintainer-kvm-x86.rst | 1 .. include:: ../disclaimer-sp.rst
3 :Original: Documentation/process/maintainer-kvm-x86.rst
10 --------
15 principiantes en algún momento. Mientras haga un esfuerzo honesto por
21 -----
26 -------
27 KVM x86 se encuentra actualmente en un período de transición de ser parte
31 x86, ``github.com/kvm-x86/linux.git``.
33 Por lo general, las correcciones para el ciclo en curso se aplican
35 para el siguiente ciclo se dirige a través del árbol de KVM x86. En el
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| /linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| H A D | nv50.c | 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
28 #include <engine/fifo.h>
35 return nvkm_rd32(gr->engine.subdev.device, 0x1540); in nv50_gr_units()
46 int ret = nvkm_gpuobj_new(object->engine->subdev.device, 16, in nv50_gr_object_bind()
50 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in nv50_gr_object_bind()
72 struct nv50_gr *gr = nv50_gr_chan(object)->gr; in nv50_gr_chan_bind()
73 int ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size, in nv50_gr_chan_bind()
77 nv50_grctx_fill(gr->base.engine.subdev.device, *pgpuobj); in nv50_gr_chan_bind()
96 return -ENOMEM; in nv50_gr_chan_new()
97 nvkm_object_ctor(&nv50_gr_chan, oclass, &chan->object); in nv50_gr_chan_new()
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| /linux/drivers/media/i2c/ |
| H A D | tc358746.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * TC358746 - Parallel <-> CSI-2 Bridge
8 * - Currently only 'Parallel-in -> CSI-out' mode is supported!
13 #include <linux/clk-provider.h>
19 #include <linux/phy/phy-mipi-dphy.h>
24 #include <media/v4l2-ctrls.h>
25 #include <media/v4l2-device.h>
26 #include <media/v4l2-fwnode.h>
27 #include <media/v4l2-mc.h>
29 /* 16-bit registers */
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | display_mode_vba_util_32.c | 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
87 p = 3 * wx - w; in dml32_dscceComputeDelay()
91 L = (ax + wx - 1) / wx; in dml32_dscceComputeDelay()
96 Delay = L * wx * (numSlices - 1) + ax + s + lstall + 22; in dml32_dscceComputeDelay()
123 // dscc - input deserializer in dml32_dscComputeDelay()
127 // dscc - input cdc fifo in dml32_dscComputeDelay()
131 // dscc - cdc uncertainty in dml32_dscComputeDelay()
133 // dscc - output cdc fifo in dml32_dscComputeDelay()
137 // dscc - cdc uncertainty in dml32_dscComputeDelay()
139 // dscc - output serializer in dml32_dscComputeDelay()
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| /linux/drivers/infiniband/hw/hfi1/ |
| H A D | chip.c | 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright(c) 2015 - 2020 Intel Corporation.
32 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
78 #define SEC_SC_HALTED 0x4 /* per-context only */
79 #define SEC_SPC_FREEZE 0x8 /* per-HFI only */
87 * 0 - User Fecn Handling
88 * 1 - Vnic
89 * 2 - AIP
90 * 3 - Verbs
101 #define emulator_rev(dd) ((dd)->irev >> 8)
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