Home
last modified time | relevance | path

Searched +full:memcpy +full:- +full:bus +full:- +full:width (Results 1 – 25 of 252) sorted by relevance

1234567891011

/linux/Documentation/devicetree/bindings/dma/
H A Darm-pl08x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/arm-pl08x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
13 - $ref: /schemas/arm/primecell.yaml#
14 - $ref: dma-controller.yaml#
22 - arm,pl080
23 - arm,pl081
25 - compatible
[all …]
H A Dlpc1850-dmamux.txt4 - compatible: "nxp,lpc1850-dmamux"
5 - reg: Memory map for accessing module
6 - #dma-cells: Should be set to <3>.
8 * 2nd cell contain the mux value (0-3) for the peripheral
11 - dma-requests: Number of DMA requests for the mux
12 - dma-masters: phandle pointing to the DMA controller
15 - dma-requests: Number of DMA requests the controller can handle
20 compatible = "nxp,lpc1850-gpdma", "arm,pl080", "arm,primecell";
21 arm,primecell-periphid = <0x00041080>;
25 clock-names = "apb_pclk";
[all …]
/linux/drivers/dma/
H A Damba-pl08x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (c) 2010 ST-Ericsson SA
23 * The PL080 has a dual bus master, PL081 has a single master.
27 * - CH_CONFIG register at different offset,
28 * - separate CH_CONTROL2 register for transfer size,
29 * - bigger maximum transfer size,
30 * - 8-word aligned LLI, instead of 4-word, due to extra CCTL2 word,
31 * - no support for peripheral flow control.
45 * (Bursts are irrelevant for mem to mem transfers - there are no burst
51 * - DMAC flow control: the transfer size defines the number of transfers
[all …]
/linux/drivers/staging/media/atomisp/pci/isp/kernels/sdis/sdis_2/
H A Dia_css_sdis2.host.c1 // SPDX-License-Identifier: GPL-2.0
29 fill_row(short *private, const short *public, unsigned int width, in fill_row() argument
32 memcpy(private, public, width * sizeof(short)); in fill_row()
33 memset(&private[width], 0, padding * sizeof(short)); in fill_row()
41 unsigned int aligned_width = from->grid.aligned_width * in ia_css_sdis2_horicoef_vmem_encode()
42 from->grid.bqs_per_grid_cell; in ia_css_sdis2_horicoef_vmem_encode()
43 unsigned int width = from->grid.num_hor_coefs; in ia_css_sdis2_horicoef_vmem_encode() local
44 int padding = aligned_width - width; in ia_css_sdis2_horicoef_vmem_encode()
55 fill_row(&private[0 * stride], from->hor_coefs.odd_real, width, padding); in ia_css_sdis2_horicoef_vmem_encode()
56 fill_row(&private[1 * stride], from->hor_coefs.odd_imag, width, padding); in ia_css_sdis2_horicoef_vmem_encode()
[all …]
/linux/Documentation/devicetree/bindings/mtd/
H A Dmtd-physmap.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/mtd-physmap.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
10 - Rob Herring <robh@kernel.org>
17 - $ref: mtd.yaml#
18 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
23 - items:
24 - enum:
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-39x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
31 #address-cells = <1>;
32 #size-cells = <0>;
33 enable-method = "marvell,armada-390-smp";
37 compatible = "arm,cortex-a9";
[all …]
H A Darmada-375.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/phy/phy.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
[all …]
H A Darmada-xp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
16 #include "armada-370-xp.dtsi"
19 #address-cells = <2>;
20 #size-cells = <2>;
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
31 compatible = "marvell,armadaxp-mbus", "simple-bus";
38 internal-regs {
40 compatible = "marvell,armada-xp-sdram-controller";
[all …]
H A Dkirkwood.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/gpio/gpio.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
11 interrupt-parent = <&intc>;
14 #address-cells = <1>;
15 #size-cells = <0>;
22 clock-names = "cpu_clk", "ddrclk", "powersave";
33 compatible = "marvell,kirkwood-mbus", "simple-bus";
[all …]
/linux/drivers/acpi/acpica/
H A Dexregion.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
4 * Module Name: exregion - ACPI default op_region (address space) handlers
6 * Copyright (C) 2000 - 2023, Intel Corp.
21 * PARAMETERS: function - Read or Write operation
22 * address - Where in the space to read or write
23 * bit_width - Field width in bits (8, 16, or 32)
24 * value - Pointer to in or out value
25 * handler_context - Pointer to Handler's context
26 * region_context - Pointer to context specific to the
44 struct acpi_mem_mapping *mm = mem_info->cur_mm; in acpi_ex_system_memory_space_handler()
[all …]
/linux/drivers/media/pci/saa7164/
H A Dsaa7164-api.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2010-2015 Steven Toth <stoth@kernellabs.com>
22 i->deviceinst = 0; in saa7164_api_get_load_info()
23 i->devicespec = 0; in saa7164_api_get_load_info()
24 i->mode = 0; in saa7164_api_get_load_info()
25 i->status = 0; in saa7164_api_get_load_info()
32 printk(KERN_INFO "saa7164[%d]-CPU: %d percent", dev->nr, i->CPULoad); in saa7164_api_get_load_info()
45 while (more--) { in saa7164_api_collect_debug()
58 printk(KERN_INFO "saa7164[%d]-FWMSG: %s", dev->nr, in saa7164_api_collect_debug()
93 struct saa7164_dev *dev = port->dev; in saa7164_api_set_vbi_format()
[all …]
/linux/drivers/net/wireless/quantenna/qtnfmac/
H A Devent.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (c) 2015-2016 Quantenna Communications. All rights reserved. */
12 #include "bus.h"
34 mac->macid, vif->vifid, len, sizeof(*sta_assoc)); in qtnf_event_handle_sta_assoc()
35 return -EINVAL; in qtnf_event_handle_sta_assoc()
38 if (vif->wdev.iftype != NL80211_IFTYPE_AP) { in qtnf_event_handle_sta_assoc()
40 mac->macid, vif->vifid); in qtnf_event_handle_sta_assoc()
41 return -EPROTO; in qtnf_event_handle_sta_assoc()
46 return -ENOMEM; in qtnf_event_handle_sta_assoc()
48 sta_addr = sta_assoc->sta_addr; in qtnf_event_handle_sta_assoc()
[all …]
/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2g.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/pinctrl/keystone.h>
10 #include <dt-bindings/gpio/gpio.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
32 #address-cells = <1>;
33 #size-cells = <0>;
[all …]
/linux/include/linux/amba/
H A Dpl08x.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/amba/pl08x.h - ARM PrimeCell DMA Controller driver
6 * Copyright (C) 2010 ST-Ericsson SA
32 * struct pl08x_channel_data - data structure to pass info between
84 * struct pl08x_platform_data - the platform configuration for the PL08x
91 * @memcpy_burst_size: the appropriate burst size for memcpy operations
92 * @memcpy_bus_width: memory bus width
93 * @memcpy_prot_buff: whether memcpy DMA is bufferable
94 * @memcpy_prot_cache: whether memcpy DMA is cacheable
/linux/drivers/memory/
H A Demif.c1 // SPDX-License-Identifier: GPL-2.0-only
33 * struct emif_data - Per device static data for driver's use
38 * to this EMIF - read from MR4 register. If there
43 * @base: base address of memory-mapped IO registers.
47 * frequencies, to avoid re-calculating them on
77 u32 type = emif->plat_data->device_info->type; in do_emif_regdump_show()
78 u32 ip_rev = emif->plat_data->ip_rev; in do_emif_regdump_show()
81 regs->freq/1000000); in do_emif_regdump_show()
83 seq_printf(s, "ref_ctrl_shdw\t: 0x%08x\n", regs->ref_ctrl_shdw); in do_emif_regdump_show()
84 seq_printf(s, "sdram_tim1_shdw\t: 0x%08x\n", regs->sdram_tim1_shdw); in do_emif_regdump_show()
[all …]
/linux/samples/vfio-mdev/
H A Dmdpy.c1 // SPDX-License-Identifier: GPL-2.0
5 * See mdpy-defs.h for device specs
30 #include "mdpy-defs.h"
54 u32 width; member
59 .type.pretty_name = MDPY_CLASS_NAME "-" MDPY_TYPE_1,
62 .width = 640,
66 .type.pretty_name = MDPY_CLASS_NAME "-" MDPY_TYPE_2,
69 .width = 1024,
73 .type.pretty_name = MDPY_CLASS_NAME "-" MDPY_TYPE_3,
76 .width = 1920,
[all …]
/linux/drivers/ssb/
H A Dsdio.c3 * SDIO-Hostbus related functions
9 * Copyright 2007-2008 Michael Buesch <m@bues.ch>
60 #define SBSDIO_FUNC1_SBADDRMID 0x1000b /* SB Address window Mid (b23-b16) */
61 #define SBSDIO_FUNC1_SBADDRHIGH 0x1000c /* SB Address window High (b24-b31) */
71 #define SBSDIO_SB_ACCESS_2_4B_FLAG 0x8000 /* forces 32-bit SB access */
78 * ------- ------- ------------------------------------------
85 * In order to access the contents of a 32-bit Silicon Backplane address
94 * a 32-bit access flag
104 static inline struct device *ssb_sdio_dev(struct ssb_bus *bus) in ssb_sdio_dev() argument
106 return &bus->host_sdio->dev; in ssb_sdio_dev()
[all …]
/linux/arch/arm/boot/dts/st/
H A Dste-nomadik-stn8815.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree for the ST-Ericsson Nomadik 8815 STn8815 SoC
6 #include <dt-bindings/gpio/gpio.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
18 L2: cache-controller {
19 compatible = "arm,l210-cache";
21 interrupt-parent = <&vica>;
23 cache-unified;
24 cache-level = <2>;
[all …]
/linux/arch/arm/boot/dts/gemini/
H A Dgemini.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/clock/cortina,gemini-clock.h>
8 #include <dt-bindings/reset/cortina,gemini-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
16 compatible = "simple-bus";
17 interrupt-parent = <&intcon>;
20 compatible = "cortina,gemini-flash", "cfi-flash";
[all …]
/linux/drivers/media/test-drivers/vimc/
H A Dvimc-scaler.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * vimc-scaler.c Virtual Media Controller Driver
5 * Copyright (C) 2015-2017 Helen Koike <helen.fornazier@gmail.com>
11 #include <linux/v4l2-mediabus.h>
12 #include <media/v4l2-rect.h>
13 #include <media/v4l2-subdev.h>
15 #include "vimc-common.h"
46 .width = VIMC_SCALER_FMT_WIDTH_DEFAULT,
54 .width = VIMC_SCALER_FMT_WIDTH_DEFAULT,
61 .width = VIMC_FRAME_MIN_WIDTH,
[all …]
/linux/drivers/mmc/core/
H A Dmmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2003-2004 Russell King, All Rights Reserved.
6 * Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
25 #include "bus.h"
59 u32 *resp = card->raw_cid; in mmc_decode_cid()
65 add_device_randomness(&card->raw_cid, sizeof(card->raw_cid)); in mmc_decode_cid()
71 switch (card->csd.mmca_vsn) { in mmc_decode_cid()
72 case 0: /* MMC v1.0 - v1.2 */ in mmc_decode_cid()
74 card->cid.manfid = unstuff_bits(resp, 104, 24); in mmc_decode_cid()
75 card->cid.prod_name[0] = unstuff_bits(resp, 96, 8); in mmc_decode_cid()
[all …]
/linux/drivers/media/platform/nxp/
H A Dimx-mipi-csis.c1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung CSIS MIPI CSI-2 receiver driver.
5 * The Samsung CSIS IP is a MIPI CSI-2 receiver found in various NXP i.MX7 and
10 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved.
11 * Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd.
31 #include <media/v4l2-common.h>
32 #include <media/v4l2-device.h>
33 #include <media/v4l2-event.h>
34 #include <media/v4l2-fwnode.h>
35 #include <media/v4l2-mc.h>
[all …]
/linux/drivers/media/platform/st/stm32/
H A Dstm32-dcmi.c1 // SPDX-License-Identifier: GPL-2.0
30 #include <media/v4l2-ctrls.h>
31 #include <media/v4l2-dev.h>
32 #include <media/v4l2-device.h>
33 #include <media/v4l2-event.h>
34 #include <media/v4l2-fwnode.h>
35 #include <media/v4l2-image-sizes.h>
36 #include <media/v4l2-ioctl.h>
37 #include <media/v4l2-rect.h>
38 #include <media/videobuf2-dma-contig.h>
[all …]
/linux/drivers/media/platform/samsung/exynos4-is/
H A Dmipi-csis.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung S5P/EXYNOS SoC series MIPI-CSI receiver driver
5 * Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd.
29 #include <media/drv-intf/exynos-fimc.h>
30 #include <media/v4l2-fwnode.h>
31 #include <media/v4l2-subdev.h>
33 #include "mipi-csis.h"
37 MODULE_PARM_DESC(debug, "Debug level (0-2)");
51 /* D-PHY control */
62 #define S5PCSIS_CFG_FMT_USER(x) ((0x30 + x - 1) << 2)
[all …]
/linux/drivers/edac/
H A Ddmc520_edac.c1 // SPDX-License-Identifier: GPL-2.0
4 * EDAC driver for DMC-520 memory controller.
25 /* DMC-520 registers */
43 /* DMC-520 types, masks and bitfields */
78 * The max-length message would be: "rank:7 bank:15 row:262143 col:1023".
79 * Max length is 34. Using a 40-size buffer is enough.
82 #define EDAC_MOD_NAME "dmc520-edac"
85 /* the data bus width for the attached memory chips. */
97 /* memory device width */
165 * error_lock is to protect concurrent writes to the mci->error_desc through
[all …]

1234567891011