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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dmediatek,syscon.yaml4 $id: http://devicetree.org/schemas/clock/mediatek,syscon.yaml#
7 title: MediaTek Clock controller syscon's
14 The MediaTek clock controller syscon's provide various clocks to the system.
21 - mediatek,mt2701-bdpsys
22 - mediatek,mt2701-imgsys
23 - mediatek,mt2701-vdecsys
24 - mediatek,mt2712-bdpsys
25 - mediatek,mt2712-imgsys
26 - mediatek,mt2712-jpgdecsys
27 - mediatek,mt2712-mcucfg
[all …]
H A Dmediatek,mt8188-clock.yaml4 $id: http://devicetree.org/schemas/clock/mediatek,mt8188-clock.yaml#
7 title: MediaTek Functional Clock Controller for MT8188
10 - Garmin Chang <garmin.chang@mediatek.com>
13 The clock architecture in MediaTek like below
25 - mediatek,mt8188-adsp-audio26m
26 - mediatek,mt8188-camsys
27 - mediatek,mt8188-camsys-rawa
28 - mediatek,mt8188-camsys-rawb
29 - mediatek,mt8188-camsys-yuva
30 - mediatek,mt8188-camsys-yuvb
[all …]
H A Dmediatek,mt8195-clock.yaml4 $id: http://devicetree.org/schemas/clock/mediatek,mt8195-clock.yaml#
7 title: MediaTek Functional Clock Controller for MT8195
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
13 The clock architecture in Mediatek like below
27 - mediatek,mt8195-scp_adsp
28 - mediatek,mt8195-imp_iic_wrap_s
29 - mediatek,mt8195-imp_iic_wrap_w
30 - mediatek,mt8195-mfgcfg
31 - mediatek,mt8195-wpesys
32 - mediatek,mt8195-wpesys_vpp0
[all …]
H A Dmediatek,mt8192-clock.yaml4 $id: http://devicetree.org/schemas/clock/mediatek,mt8192-clock.yaml#
7 title: MediaTek Functional Clock Controller for MT8192
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
13 The Mediatek functional clock controller provides various clocks on MT8192.
19 - mediatek,mt8192-scp_adsp
20 - mediatek,mt8192-imp_iic_wrap_c
21 - mediatek,mt8192-imp_iic_wrap_e
22 - mediatek,mt8192-imp_iic_wrap_s
23 - mediatek,mt8192-imp_iic_wrap_ws
24 - mediatek,mt8192-imp_iic_wrap_w
[all …]
H A Dmediatek,infracfg.yaml4 $id: http://devicetree.org/schemas/clock/mediatek,infracfg.yaml#
7 title: MediaTek Infrastructure System Configuration Controller
13 The Mediatek infracfg controller provides various clocks and reset outputs
15 and <dt-bindings/clock/mediatek,mt*-infracfg.h>, and reset values in
17 <dt-bindings/reset/mediatek,mt*-infracfg.h>.
24 - mediatek,mt2701-infracfg
25 - mediatek,mt2712-infracfg
26 - mediatek,mt6735-infracfg
27 - mediatek,mt6765-infracfg
28 - mediatek,mt6795-infracfg
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dmediatek.yaml4 $id: http://devicetree.org/schemas/arm/mediatek.yaml#
7 title: MediaTek SoC based Platforms
10 - Sean Wang <sean.wang@mediatek.com>
13 Boards with a MediaTek SoC shall have the following properties.
23 - mediatek,mt2701-evb
24 - const: mediatek,mt2701
28 - mediatek,mt2712-evb
29 - const: mediatek,mt2712
34 - const: mediatek,mt6572
37 - mediatek,mt6580-evbp1
[all …]
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dmediatek,sysirq.txt1 MediaTek sysirq
3 MediaTek SOCs sysirq support controllable irq inverter for each GIC SPI
8 "mediatek,mt8516-sysirq", "mediatek,mt6577-sysirq": for MT8516
9 "mediatek,mt8183-sysirq", "mediatek,mt6577-sysirq": for MT8183
10 "mediatek,mt8173-sysirq", "mediatek,mt6577-sysirq": for MT8173
11 "mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq": for MT8135
12 "mediatek,mt8127-sysirq", "mediatek,mt6577-sysirq": for MT8127
13 "mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq": for MT7622
14 "mediatek,mt7623-sysirq", "mediatek,mt6577-sysirq": for MT7623
15 "mediatek,mt7629-sysirq", "mediatek,mt6577-sysirq": for MT7629
[all …]
H A Dmediatek,mt6577-sysirq.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/mediatek,mt6577-sysirq.yaml#
7 title: MediaTek sysirq
10 MediaTek SOCs sysirq support controllable irq inverter for each GIC SPI
19 - const: mediatek,mt6577-sysirq
22 - mediatek,mt2701-sysirq
23 - mediatek,mt2712-sysirq
24 - mediatek,mt6572-sysirq
25 - mediatek,mt6580-sysirq
26 - mediatek,mt6582-sysirq
27 - mediatek,mt6589-sysirq
[all …]
/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Di2c-mt65xx.txt1 * MediaTek's I2C controller
3 The MediaTek's I2C controller is used to interface with I2C devices.
7 "mediatek,mt2701-i2c", "mediatek,mt6577-i2c": for MediaTek MT2701
8 "mediatek,mt2712-i2c": for MediaTek MT2712
9 "mediatek,mt6577-i2c": for MediaTek MT6577
10 "mediatek,mt6589-i2c": for MediaTek MT6589
11 "mediatek,mt6797-i2c", "mediatek,mt6577-i2c": for MediaTek MT6797
12 "mediatek,mt7622-i2c": for MediaTek MT7622
13 "mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623
14 "mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek MT7629
[all …]
H A Di2c-mt65xx.yaml7 title: MediaTek I2C controller
11 various MediaTek SoCs.
17 - Qii Wang <qii.wang@mediatek.com>
22 - const: mediatek,mt2712-i2c
23 - const: mediatek,mt6577-i2c
24 - const: mediatek,mt6589-i2c
25 - const: mediatek,mt7622-i2c
26 - const: mediatek,mt7981-i2c
27 - const: mediatek,mt7986-i2c
28 - const: mediatek,mt8168-i2c
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/mediatek/
H A Dmediatek,mt8195-clock.yaml4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#
7 title: MediaTek Functional Clock Controller for MT8195
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
13 The clock architecture in Mediatek like below
27 - mediatek,mt8195-scp_adsp
28 - mediatek,mt8195-imp_iic_wrap_s
29 - mediatek,mt8195-imp_iic_wrap_w
30 - mediatek,mt8195-mfgcfg
31 - mediatek,mt8195-wpesys
32 - mediatek,mt8195-wpesys_vpp0
[all …]
H A Dmediatek,mt8192-clock.yaml4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml#
7 title: MediaTek Functional Clock Controller for MT8192
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
13 The Mediatek functional clock controller provides various clocks on MT8192.
19 - mediatek,mt8192-scp_adsp
20 - mediatek,mt8192-imp_iic_wrap_c
21 - mediatek,mt8192-imp_iic_wrap_e
22 - mediatek,mt8192-imp_iic_wrap_s
23 - mediatek,mt8192-imp_iic_wrap_ws
24 - mediatek,mt8192-imp_iic_wrap_w
[all …]
H A Dmediatek,infracfg.yaml4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#
7 title: MediaTek Infrastructure System Configuration Controller
13 The Mediatek infracfg controller provides various clocks and reset outputs
23 - mediatek,mt2701-infracfg
24 - mediatek,mt2712-infracfg
25 - mediatek,mt6765-infracfg
26 - mediatek,mt6795-infracfg
27 - mediatek,mt6779-infracfg_ao
28 - mediatek,mt679
[all...]
/freebsd/sys/contrib/device-tree/Bindings/display/mediatek/
H A Dmediatek,disp.txt1 Mediatek display subsystem
4 The Mediatek display subsystem consists of various DISP function blocks in the
12 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml.
25 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and
26 Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml.
29 - compatible: "mediatek,<chip>-disp-<function>", one of
30 "mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc)
31 "mediatek,<chip>-disp-ovl-2l" - overlay (2 layers, blending, csc)
32 "mediatek,<chip>-disp-rdma" - read DMA / line buffer
33 "mediatek,<chip>-disp-wdma" - write DMA
[all …]
/freebsd/sys/contrib/device-tree/Bindings/iommu/
H A Dmediatek,iommu.yaml4 $id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml#
7 title: MediaTek IOMMU Architecture Implementation
10 - Yong Wu <yong.wu@mediatek.com>
13 Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and
73 - mediatek,mt2701-m4u # generation one
74 - mediatek,mt2712-m4u # generation two
75 - mediatek,mt6779-m4u # generation two
76 - mediatek,mt6795-m4u # generation two
77 - mediatek,mt6893-iommu-mm # generation two
78 - mediatek,mt8167-m4u # generation two
[all …]
/freebsd/sys/contrib/device-tree/Bindings/serial/
H A Dmediatek,uart.yaml4 $id: http://devicetree.org/schemas/serial/mediatek,uart.yaml#
7 title: MediaTek Universal Asynchronous Receiver/Transmitter (UART)
16 The MediaTek UART is based on the basic 8250 UART and compatible
23 - const: mediatek,mt6577-uart
26 - mediatek,mt2701-uart
27 - mediatek,mt2712-uart
28 - mediatek,mt6572-uart
29 - mediatek,mt6580-uart
30 - mediatek,mt6582-uart
31 - mediatek,mt6589-uart
[all …]
H A Dmtk-uart.txt1 * MediaTek Universal Asynchronous Receiver/Transmitter (UART)
5 * "mediatek,mt2701-uart" for MT2701 compatible UARTS
6 * "mediatek,mt2712-uart" for MT2712 compatible UARTS
7 * "mediatek,mt6580-uart" for MT6580 compatible UARTS
8 * "mediatek,mt6582-uart" for MT6582 compatible UARTS
9 * "mediatek,mt6589-uart" for MT6589 compatible UARTS
10 * "mediatek,mt6755-uart" for MT6755 compatible UARTS
11 * "mediatek,mt6765-uart" for MT6765 compatible UARTS
12 * "mediatek,mt6779-uart" for MT6779 compatible UARTS
13 * "mediatek,mt6795-uart" for MT6795 compatible UARTS
[all …]
/freebsd/sys/contrib/device-tree/Bindings/watchdog/
H A Dmtk-wdt.txt1 Mediatek SoCs Watchdog timer
9 "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701
10 "mediatek,mt2712-wdt": for MT2712
11 "mediatek,mt6582-wdt", "mediatek,mt6589-wdt": for MT6582
12 "mediatek,mt6589-wdt": for MT6589
13 "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797
14 "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622
15 "mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623
16 "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
17 "mediatek,mt7986-wdt", "mediatek,mt6589-wdt": for MT7986
[all …]
H A Dmediatek,mtk-wdt.yaml4 $id: http://devicetree.org/schemas/watchdog/mediatek,mtk-wdt.yaml#
7 title: MediaTek SoCs Watchdog timer
23 - mediatek,mt2712-wdt
24 - mediatek,mt6589-wdt
25 - mediatek,mt6735-wdt
26 - mediatek,mt6795-wdt
27 - mediatek,mt7986-wdt
28 - mediatek,mt7988-wdt
29 - mediatek,mt8183-wdt
30 - mediatek,mt8186-wdt
[all …]
/freebsd/sys/contrib/device-tree/src/arm/mediatek/
H A Dmt7623n.dtsi3 * Copyright © 2017-2020 MediaTek Inc.
4 * Author: Sean Wang <sean.wang@mediatek.com>
5 * Ryder Lee <ryder.lee@mediatek.com>
19 compatible = "mediatek,mt7623-g3dsys",
20 "mediatek,mt2701-g3dsys",
28 compatible = "mediatek,mt7623-mali", "arm,mali-450";
52 compatible = "mediatek,mt7623-mmsys",
53 "mediatek,mt2701-mmsys",
60 compatible = "mediatek,mt7623-smi-larb",
61 "mediatek,mt270
[all...]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dmediatek,smi-larb.yaml2 # Copyright (c) 2020 MediaTek Inc.
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-larb.yaml#
11 - Yong Wu <yong.wu@mediatek.com>
14 The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
20 - mediatek,mt2701-smi-larb
21 - mediatek,mt2712-smi-larb
22 - mediatek,mt6779-smi-larb
23 - mediatek,mt6795-smi-larb
24 - mediatek,mt6893-smi-larb
25 - mediatek,mt8167-smi-larb
[all …]
H A Dmediatek,smi-common.yaml2 # Copyright (c) 2020 MediaTek Inc.
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
11 - Yong Wu <yong.wu@mediatek.com>
14 The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
16 MediaTek SMI have two generations of HW architecture, here is the list
32 - mediatek,mt2701-smi-common
33 - mediatek,mt2712-smi-common
34 - mediatek,mt6779-smi-common
35 - mediatek,mt6795-smi-common
36 - mediatek,mt6893-smi-common
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dmtk-sd.yaml10 - Chaotian Jing <chaotian.jing@mediatek.com>
11 - Wenbin Mei <wenbin.mei@mediatek.com>
17 - mediatek,mt2701-mmc
18 - mediatek,mt2712-mmc
19 - mediatek,mt6779-mmc
20 - mediatek,mt6795-mmc
21 - mediatek,mt7620-mmc
22 - mediatek,mt7622-mmc
23 - mediatek,mt7986-mmc
24 - mediatek,mt7988-mmc
[all …]
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dmediatek,spi-mt65xx.yaml4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml#
7 title: SPI Bus controller for MediaTek ARM SoCs
10 - Leilk Liu <leilk.liu@mediatek.com>
20 - mediatek,mt7629-spi
21 - mediatek,mt8365-spi
22 - const: mediatek,mt7622-spi
25 - mediatek,mt8516-spi
26 - const: mediatek,mt2712-spi
29 - mediatek,mt6779-spi
30 - mediatek,mt8186-spi
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8188.dtsi3 * Copyright (c) 2023 MediaTek Inc.
8 #include <dt-bindings/clock/mediatek,mt8188-clk.h>
11 #include <dt-bindings/mailbox/mediatek,mt8188-gce.h>
12 #include <dt-bindings/memory/mediatek,mt8188-memory-port.h>
14 #include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
15 #include <dt-bindings/power/mediatek,mt8188-power.h>
18 #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
21 compatible = "mediatek,mt8188";
466 mediatek,platform = <&afe>;
932 compatible = "mediatek,cpufreq-hw";
[all …]

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