Home
last modified time | relevance | path

Searched full:mclk (Results 1 – 25 of 920) sorted by relevance

12345678910>>...37

/linux/drivers/clk/hisilicon/
H A Dclk-hi3620.c283 struct clk_mmc *mclk = to_mmc(hw); in mmc_clk_determine_rate() local
285 if ((req->rate <= 13000000) && (mclk->id == HI3620_MMC_CIUCLK1)) { in mmc_clk_determine_rate()
322 struct clk_mmc *mclk = to_mmc(hw); in mmc_clk_set_timing() local
359 val = readl_relaxed(mclk->clken_reg); in mmc_clk_set_timing()
360 val &= ~(1 << mclk->clken_bit); in mmc_clk_set_timing()
361 writel_relaxed(val, mclk->clken_reg); in mmc_clk_set_timing()
363 val = readl_relaxed(mclk->sam_reg); in mmc_clk_set_timing()
364 val = mmc_clk_delay(val, sam, mclk->sam_off, mclk->sam_bits); in mmc_clk_set_timing()
365 writel_relaxed(val, mclk->sam_reg); in mmc_clk_set_timing()
367 val = readl_relaxed(mclk->drv_reg); in mmc_clk_set_timing()
[all …]
/linux/drivers/gpu/drm/radeon/
H A Drv730_dpm.c118 LPRV7XX_SMC_MCLK_VALUE mclk) in rv730_populate_mclk_value() argument
183 mclk->mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in rv730_populate_mclk_value()
184 mclk->mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl); in rv730_populate_mclk_value()
185 mclk->mclk730.mclk_value = cpu_to_be32(memory_clock); in rv730_populate_mclk_value()
186 mclk->mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); in rv730_populate_mclk_value()
187 mclk->mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2); in rv730_populate_mclk_value()
188 mclk->mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3); in rv730_populate_mclk_value()
189 mclk->mclk730.vMPLL_SS = cpu_to_be32(mpll_ss); in rv730_populate_mclk_value()
190 mclk->mclk730.vMPLL_SS2 = cpu_to_be32(mpll_ss2); in rv730_populate_mclk_value()
294 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); in rv730_populate_smc_acpi_state()
[all …]
H A Drv740_dpm.c114 DRM_DEBUG_KMS("Target MCLK greater than largest MCLK in DLL speed table\n"); in rv740_get_dll_speed()
187 RV7XX_SMC_MCLK_VALUE *mclk) in rv740_populate_mclk_value() argument
274 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in rv740_populate_mclk_value()
275 mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in rv740_populate_mclk_value()
276 mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); in rv740_populate_mclk_value()
277 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in rv740_populate_mclk_value()
278 mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); in rv740_populate_mclk_value()
279 mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in rv740_populate_mclk_value()
280 mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl); in rv740_populate_mclk_value()
281 mclk->mclk770.vMPLL_SS = cpu_to_be32(mpll_ss1); in rv740_populate_mclk_value()
[all …]
H A Drv770_dpm.c389 RV7XX_SMC_MCLK_VALUE *mclk) in rv770_populate_mclk_value() argument
474 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in rv770_populate_mclk_value()
475 mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in rv770_populate_mclk_value()
476 mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); in rv770_populate_mclk_value()
477 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in rv770_populate_mclk_value()
478 mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); in rv770_populate_mclk_value()
479 mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in rv770_populate_mclk_value()
480 mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl); in rv770_populate_mclk_value()
593 int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, in rv770_populate_mvdd_value() argument
604 if (mclk <= pi->mvdd_split_frequency) { in rv770_populate_mvdd_value()
[all …]
H A Dcypress_dpm.c422 u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) in cypress_get_strobe_mode_settings() argument
429 if (mclk <= pi->mclk_strobe_mode_threshold) in cypress_get_strobe_mode_settings()
431 result = cypress_get_mclk_frequency_ratio(rdev, mclk, strobe_mode); in cypress_get_strobe_mode_settings()
474 RV7XX_SMC_MCLK_VALUE *mclk, in cypress_populate_mclk_value() argument
600 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in cypress_populate_mclk_value()
601 mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in cypress_populate_mclk_value()
602 mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); in cypress_populate_mclk_value()
603 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in cypress_populate_mclk_value()
604 mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); in cypress_populate_mclk_value()
605 mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in cypress_populate_mclk_value()
[all …]
H A Dbtc_dpm.c1214 u32 *sclk, u32 *mclk) in btc_skip_blacklist_clocks() argument
1218 if ((sclk == NULL) || (mclk == NULL)) in btc_skip_blacklist_clocks()
1225 (btc_blacklist_clocks[i].mclk == *mclk)) in btc_skip_blacklist_clocks()
1234 btc_skip_blacklist_clocks(rdev, max_sclk, max_mclk, sclk, mclk); in btc_skip_blacklist_clocks()
1244 if ((pl->mclk == 0) || (pl->sclk == 0)) in btc_adjust_clock_combinations()
1247 if (pl->mclk == pl->sclk) in btc_adjust_clock_combinations()
1250 if (pl->mclk > pl->sclk) { in btc_adjust_clock_combinations()
1251 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio) in btc_adjust_clock_combinations()
1254 (pl->mclk + in btc_adjust_clock_combinations()
1258 if ((pl->sclk - pl->mclk) > rdev->pm.dpm.dyn_state.sclk_mclk_delta) in btc_adjust_clock_combinations()
[all …]
/linux/sound/soc/qcom/qdsp6/
H A Dq6prm.h67 /* Clock ID for MCLK for WSA2 core */
69 /* Clock ID for NPL MCLK for WSA2 core */
71 /* Clock ID for RX Core TX MCLK */
73 /* Clock ID for RX CORE TX 2X MCLK */
75 /* Clock ID for WSA core TX MCLK */
77 /* Clock ID for WSA core TX 2X MCLK */
79 /* Clock ID for WSA2 core TX MCLK */
81 /* Clock ID for WSA2 core TX 2X MCLK */
83 /* Clock ID for RX CORE MCLK2 2X MCLK */
/linux/sound/soc/mxs/
H A Dmxs-saif.c54 saif->mclk = freq; in mxs_saif_set_dai_sysclk()
74 * Set SAIF clock and MCLK
77 unsigned int mclk, in mxs_saif_set_clk() argument
84 dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate); in mxs_saif_set_clk()
109 * If MCLK is used, the SAIF clk ratio needs to match mclk ratio. in mxs_saif_set_clk()
113 * If MCLK is not used, we just set saif clk to 512*fs. in mxs_saif_set_clk()
120 switch (mclk / rate) { in mxs_saif_set_clk()
137 /* SAIF MCLK should be a sub-rate of 512x or 384x */ in mxs_saif_set_clk()
159 * Program the over-sample rate for MCLK output in mxs_saif_set_clk()
161 * The available MCLK range is 32x, 48x... 512x. The rate in mxs_saif_set_clk()
[all …]
/linux/sound/soc/intel/boards/
H A Dcht_bsw_rt5672.c27 /* The platform clock #3 outputs 19.2Mhz clock to codec as I2S MCLK */
34 struct clk *mclk; member
66 if (ctx->mclk) { in platform_clock_control()
67 ret = clk_prepare_enable(ctx->mclk); in platform_clock_control()
70 "could not configure MCLK state"); in platform_clock_control()
75 /* set codec PLL source to the 19.2MHz platform clock (MCLK) */ in platform_clock_control()
92 * PLL will be off when idle and MCLK will also be off by ACPI in platform_clock_control()
103 if (ctx->mclk) in platform_clock_control()
104 clk_disable_unprepare(ctx->mclk); in platform_clock_control()
166 /* set codec PLL source to the 19.2MHz platform clock (MCLK) */ in cht_aif1_hw_params()
[all …]
H A Dsof_rt5682.c34 /* Default: MCLK on, MCLK 19.2M, SSP0 */
152 dev_err(rtd->dev, "invalid mclk freq %d\n", mclk_freq); in sof_rt5682_codec_init()
156 /* need to enable ASRC function for 24MHz mclk rate */ in sof_rt5682_codec_init()
201 ret = clk_prepare_enable(ctx->rt5682.mclk); in sof_rt5682_codec_init()
203 clk_disable_unprepare(ctx->rt5682.mclk); in sof_rt5682_codec_init()
205 ret = clk_set_rate(ctx->rt5682.mclk, 19200000); in sof_rt5682_codec_init()
208 dev_err(rtd->dev, "unable to set MCLK rate\n"); in sof_rt5682_codec_init()
264 ret = clk_prepare_enable(ctx->rt5682.mclk); in sof_rt5682_hw_params()
267 "could not configure MCLK state"); in sof_rt5682_hw_params()
288 /* get the tplg configured mclk. */ in sof_rt5682_hw_params()
[all …]
H A Dcht_bsw_max98090_ti.c36 struct clk *mclk; member
62 ret = clk_prepare_enable(ctx->mclk); in platform_clock_control()
65 "could not configure MCLK state"); in platform_clock_control()
69 clk_disable_unprepare(ctx->mclk); in platform_clock_control()
239 ret = clk_prepare_enable(ctx->mclk); in cht_codec_init()
241 clk_disable_unprepare(ctx->mclk); in cht_codec_init()
243 ret = clk_set_rate(ctx->mclk, CHT_PLAT_CLK_3_HZ); in cht_codec_init()
246 dev_err(runtime->dev, "unable to set MCLK rate\n"); in cht_codec_init()
574 drv->mclk = devm_clk_get(dev, mclk_name); in snd_cht_mc_probe()
575 if (IS_ERR(drv->mclk)) { in snd_cht_mc_probe()
[all …]
/linux/sound/soc/codecs/
H A Des8311.c31 struct clk *mclk; member
326 unsigned int mclk; member
337 * settings. Internal mclk dividers and multipliers are dynamically adjusted to
340 * All rates are supported when mclk/rate ratio is 32, 64, 128, 256, 384 or 512
341 * (upper limit due to max mclk freq of 49.2MHz).
371 * If mclk_freq is a valid multiple or factor of coeff mclk freq, return 0 and
386 if (coeff->mclk == mclk_freq) { in es8311_cmp_adj_mclk_coeff()
388 } else if (mclk_freq % coeff->mclk == 0) { in es8311_cmp_adj_mclk_coeff()
389 div = mclk_freq / coeff->mclk; in es8311_cmp_adj_mclk_coeff()
393 } else if (coeff->mclk % mclk_freq == 0) { in es8311_cmp_adj_mclk_coeff()
[all …]
H A Dnau8325.c25 /* Range of Master Clock MCLK (Hz) */
29 /* scaling for MCLK source */
35 /* from MCLK input */
70 /* { FS, range, max, { MCLK source }} */
344 int mclk, int *n2_sel) in nau8325_clksrc_n2() argument
350 mclk_src = mclk >> mclk_n2_div[i].param; in nau8325_clksrc_n2()
389 int i, j, mclk, mclk_max, ratio, ratio_sel, n2_max; in nau8325_clksrc_choose() local
391 if (!nau8325->mclk || !nau8325->fs) in nau8325_clksrc_choose()
399 /* First check clock from MCLK directly, decide N2 for MCLK_SRC. in nau8325_clksrc_choose()
402 ratio = nau8325_clksrc_n2(nau8325, *srate_table, nau8325->mclk, n2_sel); in nau8325_clksrc_choose()
[all …]
H A Dwm8731.c229 u32 mclk; member
237 /* codec mclk clock divider coefficients */
302 static inline int get_coeff(int mclk, int rate) in get_coeff() argument
307 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk) in get_coeff()
371 if (wm8731->mclk && clk_set_rate(wm8731->mclk, freq)) in wm8731_set_dai_sysclk()
473 if (wm8731->mclk) { in wm8731_set_bias_level()
474 ret = clk_prepare_enable(wm8731->mclk); in wm8731_set_bias_level()
496 if (wm8731->mclk) in wm8731_set_bias_level()
497 clk_disable_unprepare(wm8731->mclk); in wm8731_set_bias_level()
570 wm8731->mclk = devm_clk_get(dev, "mclk"); in wm8731_init()
[all …]
H A Dsti-sas.c54 int mclk; member
59 int mclk; member
248 * get MCLK input frequency to check that MCLK-FS ratio is coherent
264 drvdata->spdif.mclk = freq; in sti_sas_set_sysclk()
268 drvdata->dac.mclk = freq; in sti_sas_set_sysclk()
284 if ((drvdata->spdif.mclk / runtime->rate) != 128) { in sti_sas_prepare()
285 dev_err(component->dev, "unexpected mclk-fs ratio\n"); in sti_sas_prepare()
290 if ((drvdata->dac.mclk / runtime->rate) != 256) { in sti_sas_prepare()
291 dev_err(component->dev, "unexpected mclk-fs ratio\n"); in sti_sas_prepare()
/linux/include/dt-bindings/sound/
H A Dqcom,q6dsp-lpass-ports.h205 /* Clock ID for MCLK for WSA2 core */
207 /* Clock ID for NPL MCLK for WSA2 core */
209 /* Clock ID for RX Core TX MCLK */
211 /* Clock ID for RX CORE TX 2X MCLK */
213 /* Clock ID for WSA core TX MCLK */
215 /* Clock ID for WSA core TX 2X MCLK */
217 /* Clock ID for WSA2 core TX MCLK */
219 /* Clock ID for WSA2 core TX 2X MCLK */
221 /* Clock ID for RX CORE MCLK2 2X MCLK */
/linux/drivers/clk/
H A Dclk-lochnagar.c50 LN_PARENT("ln-spdif-mclk"),
51 LN_PARENT("ln-psia1-mclk"),
52 LN_PARENT("ln-psia2-mclk"),
67 LN_PARENT("ln-spdif-mclk"),
77 LN_PARENT("ln-psia1-mclk"),
78 LN_PARENT("ln-psia2-mclk"),
80 LN_PARENT("ln-adat-mclk"),
115 LN2_CLK(PSIA1_MCLK, "ln-psia1-mclk"),
116 LN2_CLK(PSIA2_MCLK, "ln-psia2-mclk"),
117 LN2_CLK(SPDIF_MCLK, "ln-spdif-mclk"),
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dmt8173-rt5650.txt16 - mediatek,mclk: the MCLK source
17 0 : external oscillator, MCLK = 12.288M
18 1 : internal source from mt8173, MCLK = sampling rate*256
26 mediatek,mclk = <0>;
H A Deverest,es8375.yaml24 - description: clock for master clock (MCLK)
28 - const: mclk
38 everest,mclk-src:
41 Represents the MCLK/SCLK pair pins used as the internal clock.
42 0 represents selecting MCLK.
/linux/sound/soc/stm/
H A Dstm32_sai_sub.c79 * @sai_mclk: master clock from SAI mclk provider
417 * - mclk on or spdif: in stm32_sai_set_parent_rate()
418 * f_sai_ck = MCKDIV * mclk-fs * fs in stm32_sai_set_parent_rate()
419 * Here typical 256 ratio is assumed for mclk-fs in stm32_sai_set_parent_rate()
420 * - mclk off: in stm32_sai_set_parent_rate()
495 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); in stm32_sai_mclk_round_rate() local
496 struct stm32_sai_sub_data *sai = mclk->sai_data; in stm32_sai_mclk_round_rate()
503 mclk->freq = *prate / div; in stm32_sai_mclk_round_rate()
505 return mclk->freq; in stm32_sai_mclk_round_rate()
511 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); in stm32_sai_mclk_recalc_rate() local
[all …]
/linux/drivers/media/dvb-frontends/
H A Dstv0900_sw.c42 max_carrier /= intp->mclk / 1000; in stv0900_check_signal_presence()
69 max_carrier /= intp->mclk / 1000; in stv0900_get_sw_loop_params()
75 freq_inc /= intp->mclk >> 10; in stv0900_get_sw_loop_params()
135 max_carrier /= intp->mclk / 1000; in stv0900_search_carr_sw_loop()
295 u32 mclk, in stv0900_get_symbol_rate() argument
310 intval1 = (mclk) >> 16; in stv0900_get_symbol_rate()
313 rem1 = (mclk) % 0x10000; in stv0900_get_symbol_rate()
323 u32 mclk, u32 srate, in stv0900_set_symbol_rate() argument
328 dprintk("%s: Mclk %d, SR %d, Dmd %d\n", __func__, mclk, in stv0900_set_symbol_rate()
333 symb /= (mclk >> 12); in stv0900_set_symbol_rate()
[all …]
/linux/arch/powerpc/boot/dts/
H A Dmpc5121.dtsi164 clock-names = "ipg", "ips", "sys", "ref", "mclk";
176 clock-names = "ipg", "ips", "sys", "ref", "mclk";
250 clock-names = "ipg", "ips", "sys", "ref", "mclk";
262 clock-names = "ipg", "ips", "sys", "ref", "mclk";
357 clock-names = "ipg", "mclk";
369 clock-names = "ipg", "mclk";
381 clock-names = "ipg", "mclk";
393 clock-names = "ipg", "mclk";
405 clock-names = "ipg", "mclk";
417 clock-names = "ipg", "mclk";
[all …]
/linux/sound/soc/cirrus/
H A Dep93xx-i2s.c74 struct clk *mclk; member
101 clk_prepare_enable(info->mclk); in ep93xx_i2s_enable()
148 clk_disable_unprepare(info->mclk); in ep93xx_i2s_disable()
319 * 32, 64, 128. MCLK / SCLK value can be 2 and 4. in ep93xx_i2s_hw_params()
325 div = clk_get_rate(info->mclk) / params_rate(params); in ep93xx_i2s_hw_params()
335 err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv); in ep93xx_i2s_hw_params()
356 return clk_set_rate(info->mclk, freq); in ep93xx_i2s_set_sysclk()
449 info->mclk = clk_get(&pdev->dev, "mclk"); in ep93xx_i2s_probe()
450 if (IS_ERR(info->mclk)) { in ep93xx_i2s_probe()
451 err = PTR_ERR(info->mclk); in ep93xx_i2s_probe()
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a-kontron-sl28-var3-ads2.dts53 simple-audio-card,mclk-fs = <256>;
111 clocks = <&mclk>;
112 clock-names = "mclk";
113 assigned-clocks = <&mclk>;
132 mclk: clock-mclk@f130080 { label
/linux/drivers/iio/adc/
H A Dad7766.c38 struct clk *mclk; member
97 ret = clk_prepare_enable(ad7766->mclk); in ad7766_preenable()
99 dev_err(&ad7766->spi->dev, "Failed to enable MCLK: %d\n", ret); in ad7766_preenable()
121 clk_disable_unprepare(ad7766->mclk); in ad7766_postdisable()
143 *val = clk_get_rate(ad7766->mclk) / in ad7766_read_raw()
224 ad7766->mclk = devm_clk_get(&spi->dev, "mclk"); in ad7766_probe()
225 if (IS_ERR(ad7766->mclk)) in ad7766_probe()
226 return PTR_ERR(ad7766->mclk); in ad7766_probe()

12345678910>>...37