Lines Matching full:mclk
28 /* The platform clock #3 outputs 19.2Mhz clock to codec as I2S MCLK */
35 struct clk *mclk; member
67 if (ctx->mclk) { in platform_clock_control()
68 ret = clk_prepare_enable(ctx->mclk); in platform_clock_control()
71 "could not configure MCLK state"); in platform_clock_control()
76 /* set codec PLL source to the 19.2MHz platform clock (MCLK) */ in platform_clock_control()
93 * PLL will be off when idle and MCLK will also be off by ACPI in platform_clock_control()
104 if (ctx->mclk) in platform_clock_control()
105 clk_disable_unprepare(ctx->mclk); in platform_clock_control()
167 /* set codec PLL source to the 19.2MHz platform clock (MCLK) */ in cht_aif1_hw_params()
243 if (ctx->mclk) { in cht_codec_init()
254 ret = clk_prepare_enable(ctx->mclk); in cht_codec_init()
256 clk_disable_unprepare(ctx->mclk); in cht_codec_init()
258 ret = clk_set_rate(ctx->mclk, CHT_PLAT_CLK_3_HZ); in cht_codec_init()
261 dev_err(runtime->dev, "unable to set MCLK rate\n"); in cht_codec_init()
503 drv->mclk = devm_clk_get(&pdev->dev, "pmc_plt_clk_3"); in snd_cht_mc_probe()
504 if (IS_ERR(drv->mclk)) { in snd_cht_mc_probe()
506 "Failed to get MCLK from pmc_plt_clk_3: %ld\n", in snd_cht_mc_probe()
507 PTR_ERR(drv->mclk)); in snd_cht_mc_probe()
508 return PTR_ERR(drv->mclk); in snd_cht_mc_probe()