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/linux/sound/soc/qcom/qdsp6/
H A Dq6prm.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 /* Clock ID for Primary I2S IBIT */
8 /* Clock ID for Primary I2S EBIT */
10 /* Clock ID for Secondary I2S IBIT */
12 /* Clock ID for Secondary I2S EBIT */
14 /* Clock ID for Tertiary I2S IBIT */
16 /* Clock ID for Tertiary I2S EBIT */
18 /* Clock ID for Quartnery I2S IBIT */
20 /* Clock ID for Quartnery I2S EBIT */
22 /* Clock ID for Speaker I2S IBIT */
[all …]
/linux/include/dt-bindings/sound/
H A Dqcom,q6dsp-lpass-ports.h1 /* SPDX-License-Identifier: GPL-2.0 */
205 /* Clock ID for MCLK for WSA2 core */
207 /* Clock ID for NPL MCLK for WSA2 core */
209 /* Clock ID for RX Core TX MCLK */
211 /* Clock ID for RX CORE TX 2X MCLK */
213 /* Clock ID for WSA core TX MCLK */
215 /* Clock ID for WSA core TX 2X MCLK */
217 /* Clock ID for WSA2 core TX MCLK */
219 /* Clock ID for WSA2 core TX 2X MCLK */
221 /* Clock ID for RX CORE MCLK2 2X MCLK */
/linux/include/linux/firmware/imx/
H A Dsm.h1 /* SPDX-License-Identifier: GPL-2.0+ */
16 #define SCMI_IMX95_CTRL_SAI1_MCLK 2 /* AON SAI1 MCLK */
17 #define SCMI_IMX95_CTRL_SAI3_MCLK 3 /* WAKE SAI3 MCLK */
18 #define SCMI_IMX95_CTRL_SAI4_MCLK 4 /* WAKE SAI4 MCLK */
19 #define SCMI_IMX95_CTRL_SAI5_MCLK 5 /* WAKE SAI5 MCLK */
24 #define SCMI_IMX94_CTRL_SAI1_MCLK 3U /*!< AON SAI1 MCLK */
25 #define SCMI_IMX94_CTRL_SAI2_MCLK 4U /*!< WAKE SAI2 MCLK */
26 #define SCMI_IMX94_CTRL_SAI3_MCLK 5U /*!< WAKE SAI3 MCLK */
27 #define SCMI_IMX94_CTRL_SAI4_MCLK 6U /*!< WAKE SAI4 MCLK */
30 int scmi_imx_misc_ctrl_get(u32 id, u32 *num, u32 *val);
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/linux/sound/soc/mxs/
H A Dmxs-saif.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/dma-mapping.h>
13 #include <linux/clk-provider.h>
22 #include "mxs-saif.h"
32 * For MXS, two SAIF modules are instantiated on-chip.
34 * mode simultaneously if they are connected to different off-chip codecs.
43 * The master id is provided in mach-specific layer according to different
54 saif->mclk = freq; in mxs_saif_set_dai_sysclk()
57 return -EINVAL; in mxs_saif_set_dai_sysclk()
70 return mxs_saif[saif->master_id]; in mxs_saif_get_master()
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/linux/drivers/clk/
H A Dclk-lochnagar.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2017-2018 Cirrus Logic, Inc. and
11 #include <linux/clk-provider.h>
22 #include <dt-bindings/clock/lochnagar.h>
49 LN_PARENT("ln-none"),
50 LN_PARENT("ln-spdif-mclk"),
51 LN_PARENT("ln-psia1-mclk"),
52 LN_PARENT("ln-psia2-mclk"),
53 LN_PARENT("ln-cdc-clkout"),
54 LN_PARENT("ln-dsp-clkout"),
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/linux/drivers/clk/hisilicon/
H A Dclk-hi3620.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2012-2013 Hisilicon Limited.
6 * Copyright (c) 2012-2013 Linaro Limited.
13 #include <linux/clk-provider.h>
19 #include <dt-bindings/clock/hi3620-clock.h>
216 CLK_OF_DECLARE(hi3620_clk, "hisilicon,hi3620-clock", hi3620_clk_init);
219 unsigned int id; member
238 u32 id; member
283 struct clk_mmc *mclk = to_mmc(hw); in mmc_clk_determine_rate() local
285 if ((req->rate <= 13000000) && (mclk->id == HI3620_MMC_CIUCLK1)) { in mmc_clk_determine_rate()
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/linux/arch/powerpc/platforms/512x/
H A Dclock-commonclk.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/mpc512x-clock.h>
25 /* helpers to keep the MCLK intermediates "somewhere" in our table */
61 /* intermediates for the mux+gate+div+mux MCLK generation */
89 * interpretation, no CFM, different fourth PSC/CAN mux0 input -- yet
292 val &= (1 << len) - 1; in get_bit_field()
305 spmf = get_bit_field(&clkregs->spmr, 24, 4); in get_spmf_mult()
326 divcode = get_bit_field(&clkregs->scfr2, 26, 6); in get_sys_div_x2()
350 cpmf = get_bit_field(&clkregs->spmr, 16, 4); in get_cpmf_mult_x2()
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/linux/sound/soc/intel/boards/
H A Dcht_bsw_rt5645.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * cht-bsw-rt5645.c - ASoc Machine driver for Intel Cherryview-based platforms
25 #include <sound/soc-acpi.h>
27 #include "../atom/sst-atom-controls.h"
28 #include "../common/soc-intel-quirks.h"
31 #define CHT_CODEC_DAI1 "rt5645-aif1"
32 #define CHT_CODEC_DAI2 "rt5645-aif2"
43 struct clk *mclk; member
69 struct snd_soc_dapm_context *dapm = w->dapm; in platform_clock_control()
70 struct snd_soc_card *card = dapm->card; in platform_clock_control()
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H A Dcht_bsw_rt5672.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * cht_bsw_rt5672.c - ASoc Machine driver for Intel Cherryview-based platforms
22 #include <sound/soc-acpi.h>
24 #include "../atom/sst-atom-controls.h"
25 #include "../common/soc-intel-quirks.h"
28 /* The platform clock #3 outputs 19.2Mhz clock to codec as I2S MCLK */
30 #define CHT_CODEC_DAI "rt5670-aif1"
35 struct clk *mclk; member
54 struct snd_soc_dapm_context *dapm = w->dapm; in platform_clock_control()
55 struct snd_soc_card *card = dapm->card; in platform_clock_control()
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H A Dsof_board_helpers.h1 /* SPDX-License-Identifier: GPL-2.0-only */
10 #include <sound/soc-acpi-intel-ssp-common.h>
90 * @mclk_en: true for mclk pin is connected
101 * @mclk: mclk clock data
103 * @mclk_en: true for mclk pin is connected
106 struct clk *mclk; member
123 * @ssp_mask_hdmi_in: ssp port mask of HDMI-IN BE link
129 * @link_id_overwrite: custom DAI link ID
156 * A variable stores id for all BE DAI links, use SOF_LINK_IDS macro to
157 * build the value; use DAI link array index as id if zero.
H A Dbytcr_rt5651.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * bytcr_rt5651.c - ASoc Machine driver for Intel Byt CR platform
29 #include <sound/soc-acpi.h>
31 #include "../atom/sst-atom-controls.h"
32 #include "../common/soc-intel-quirk
84 struct clk *mclk; global() member
370 byt_rt5651_pov_p1006w_quirk_cb(const struct dmi_system_id * id) byt_rt5651_pov_p1006w_quirk_cb() argument
377 byt_rt5651_quirk_cb(const struct dmi_system_id * id) byt_rt5651_quirk_cb() argument
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H A Dbytcr_wm5102.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * bytcr_wm5102.c - ASoc Machine driver for Intel Baytrail platforms with a
8 * Copyright (C) 2014-2020 Intel Corp
27 #include <sound/soc-acpi.h>
29 #include "../atom/sst-atom-controls.h"
36 struct clk *mclk; member
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/linux/sound/soc/codecs/
H A Dsti-sas.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <sound/soc-dapm.h>
20 /* sysconf 5041: Audio-Gue-Control */
22 /* sysconf 5042: Audio-DAC-Control */
54 int mclk; member
59 int mclk; member
84 status = regmap_read(drvdata->dac.regmap, reg, &val); in sti_sas_read_reg()
96 return regmap_write(drvdata->dac.regmap, reg, value); in sti_sas_write_reg()
108 /* Initialise bi-phase formatter to disabled */ in sti_sas_init_sas_registers()
113 /* Initialise bi-phase formatter idle value to 0 */ in sti_sas_init_sas_registers()
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H A Dcs42l73.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * cs42l73.c -- CS42L73 ALSA Soc Audio driver
26 #include <sound/soc-dapm.h>
49 u32 mclk; member
54 { 6, 0xF1 }, /* r06 - Power Ctl 1 */
55 { 7, 0xDF }, /* r07 - Power Ctl 2 */
56 { 8, 0x3F }, /* r08 - Power Ctl 3 */
57 { 9, 0x50 }, /* r09 - Charge Pump Freq */
58 { 10, 0x53 }, /* r0A - Output Load MicBias Short Detect */
59 { 11, 0x00 }, /* r0B - DMIC Master Clock Ctl */
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H A Dwm2000.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm2000.c -- WM2000 ALSA Soc Audio driver
5 * Copyright 2008-2011 Wolfson Microelectronics PLC.
13 * system-specific calibration information. If supplied as a
14 * sequence of ASCII-encoded hexidecimal bytes this can be converted
17 * perl -e 'while (<>) { s/[\r\n]+// ; printf("%c", hex($_)); }'
63 struct clk *mclk; member
85 return regmap_write(wm2000->regmap, reg, value); in wm2000_write()
90 struct i2c_client *i2c = wm2000->i2c; in wm2000_reset()
96 wm2000->anc_mode = ANC_OFF; in wm2000_reset()
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/linux/drivers/iio/adc/
H A Dad7766.c1 // SPDX-License-Identifier: GPL-2.0-or-later
38 struct clk *mclk; member
58 * analog performance. Both parts will use the same ID.
69 struct iio_dev *indio_dev = pf->indio_dev; in ad7766_trigger_handler()
73 ret = spi_sync(ad7766->spi, &ad7766->msg); in ad7766_trigger_handler()
77 iio_push_to_buffers_with_timestamp(indio_dev, ad7766->data, in ad7766_trigger_handler()
78 pf->timestamp); in ad7766_trigger_handler()
80 iio_trigger_notify_done(indio_dev->trig); in ad7766_trigger_handler()
90 ret = regulator_bulk_enable(ARRAY_SIZE(ad7766->reg), ad7766->reg); in ad7766_preenable()
92 dev_err(&ad7766->spi->dev, "Failed to enable supplies: %d\n", in ad7766_preenable()
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/linux/drivers/i2c/busses/
H A Di2c-sh7760.c4 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
22 #include <asm/i2c-sh7760.h>
43 #define MCR_MDBS 0x80 /* non-fifo mode switch */
104 __raw_writel(val, (unsigned long)cam->iobase + reg); in OUT32()
109 return __raw_readl((unsigned long)cam->iobase + reg); in IN32()
114 struct cami2c *id = ptr; in sh7760_i2c_irq() local
115 struct i2c_msg *msg = id->msg; in sh7760_i2c_irq()
116 char *data = msg->buf; in sh7760_i2c_irq()
119 msr = IN32(id, I2CMSR); in sh7760_i2c_irq()
120 fsr = IN32(id, I2CFSR); in sh7760_i2c_irq()
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/linux/Documentation/devicetree/bindings/sound/
H A Deverest,es8375.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/everest,es8375.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Zhang <zhangyi@everest-semi.com>
13 - $ref: dai-common.yaml#
24 - description: clock for master clock (MCLK)
26 clock-names:
28 - const: mclk
30 vdda-supply:
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H A Dloongson,ls-audio-card.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/loongson,ls-audio-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yingkun Meng <mengyingkun@loongson.cn>
19 const: loongson,ls-audio-card
25 mclk-fs:
26 $ref: simple-card.yaml#/definitions/mclk-fs
33 sound-dai:
36 - sound-dai
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H A Dmediatek,mt8173-afe-pcm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mediatek,mt8173-afe-pcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Trevor Wu <trevor.wu@mediatek.com>
14 const: mediatek,mt8173-afe-pcm
24 - description: audio infra sys clock
25 - description: audio top mux
26 - description: audio intbus mux
27 - description: apll1 clock
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/linux/sound/soc/stm/
H A Dstm32_sai_sub.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
10 #include <linux/clk-provider.h>
41 #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK)
42 #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE)
47 #define STM_SAI_IS_SUB_A(x) ((x)->id
117 unsigned int id; global() member
495 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); stm32_sai_mclk_determine_rate() local
513 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); stm32_sai_mclk_recalc_rate() local
521 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); stm32_sai_mclk_set_rate() local
540 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); stm32_sai_mclk_enable() local
551 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); stm32_sai_mclk_disable() local
570 struct stm32_sai_mclk_data *mclk; stm32_sai_add_mclk_provider() local
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/linux/include/sound/sof/
H A Ddai-intel.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
39 /* mclk 0 disable */
41 /* mclk 1 disable */
43 /* mclk keep active */
51 /* mclk early start */
55 /* mclk always on */
61 /* SSP Configuration Request - SOF_IPC_DAI_SSP_CONFIG */
67 uint32_t mclk_rate; /* mclk frequency in Hz */
81 /* MCLK */
93 /* HDA Configuration Request - SOF_IPC_DAI_HDA_CONFIG */
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/linux/drivers/mfd/
H A Dsm501.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <linux/platform_data/i2c-gpio.h>
25 #include <linux/sm501-regs.h>
135 unsigned long misct = smc501_readl(sm->regs + SM501_MISC_TIMING); in sm501_dump_clk()
136 unsigned long pm0 = smc501_readl(sm->regs + SM501_POWER_MODE_0_CLOCK); in sm501_dump_clk()
137 unsigned long pm1 = smc501_readl(sm->regs + SM501_POWER_MODE_1_CLOCK); in sm501_dump_clk()
138 unsigned long pmc = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL); in sm501_dump_clk()
163 dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n", in sm501_dump_clk()
166 dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n", in sm501_dump_clk()
169 dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1); in sm501_dump_clk()
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/linux/sound/soc/dwc/
H A Ddwc-i2s.c47 i2s_write_reg(dev->i2s_base, TER(i), 0); in i2s_disable_channels()
50 i2s_write_reg(dev->i2s_base, RER(i), 0); in i2s_disable_channels()
60 i2s_read_reg(dev->i2s_base, TOR(i)); in i2s_clear_irqs()
63 i2s_read_reg(dev->i2s_base, ROR(i)); in i2s_clear_irqs()
74 irq = i2s_read_reg(dev->i2s_base, IMR(i)); in i2s_disable_irqs()
75 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30); in i2s_disable_irqs()
79 irq = i2s_read_reg(dev->i2s_base, IMR(i)); in i2s_disable_irqs()
80 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03); in i2s_disable_irqs()
92 irq = i2s_read_reg(dev->i2s_base, IMR(i)); in i2s_enable_irqs()
93 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30); in i2s_enable_irqs()
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/linux/Documentation/devicetree/bindings/clock/
H A Dcirrus,lochnagar.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/cirrus,lochnagar.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
15 Logic devices on mini-cards, as well as allowing connection of various
25 [1] Clock : ../clock/clock-bindings.txt
28 [2] include/dt-bindings/clock/lochnagar.h
36 - cirrus,lochnagar1-clk
37 - cirrus,lochnagar2-clk
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