Lines Matching +full:mclk +full:- +full:id

1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright 2021-2022 Deqx Pty Ltd
25 static const DECLARE_TLV_DB_SCALE(src_tlv, -12750, 50, 0);
100 SND_SOC_DAPM_INPUT("MCLK"),
132 /* SRC mclk selection */
133 {"SRC mclk source", "Master (MCLK)", "MCLK"},
134 {"SRC mclk source", "Master (RXCLKI)", "RXMCLKI"},
135 {"SRC mclk source", "Recovered receiver clk", "RXMCLKO"},
156 struct snd_soc_component *component = dai->component;
163 src4xxx->master[dai->id] = true;
167 src4xxx->master[dai->id] = false;
170 return -EINVAL;
185 return -EINVAL;
193 return -EINVAL;
197 regmap_update_bits(src4xxx->regmap, SRC4XXX_BUS_FMT(dai->id),
206 struct snd_soc_component *component = codec_dai->component;
209 dev_info(component->dev, "changing mclk rate from %d to %d Hz\n",
210 src4xxx->mclk_hz, freq);
211 src4xxx->mclk_hz = freq;
220 struct snd_soc_component *component = dai->component;
227 switch (dai->id) {
236 if (src4xxx->master[dai->id]) {
237 mclk_div = src4xxx->mclk_hz/params_rate(params);
238 if (src4xxx->mclk_hz != mclk_div*params_rate(params)) {
239 dev_err(component->dev,
240 "mclk %d / rate %d has a remainder.\n",
241 src4xxx->mclk_hz, params_rate(params));
242 return -EINVAL;
245 val = ((int)mclk_div - 128) / 128;
247 dev_err(component->dev,
250 dev_err(component->dev,
252 params_rate(params), src4xxx->mclk_hz);
253 return -EINVAL;
257 ret = regmap_update_bits(src4xxx->regmap,
261 dev_err(component->dev,
269 switch (src4xxx->mclk_hz) {
284 * -Wsometimes-uninitialized from clang.
286 dev_info(component->dev,
293 ret = regmap_write(src4xxx->regmap, SRC4XXX_RCV_PLL_0F, pj);
295 dev_err(component->dev,
298 ret = regmap_write(src4xxx->regmap, SRC4XXX_RCV_PLL_10, jd);
300 dev_err(component->dev,
303 ret = regmap_write(src4xxx->regmap, SRC4XXX_RCV_PLL_11, d);
305 dev_err(component->dev,
309 ret = regmap_update_bits(src4xxx->regmap,
313 dev_err(component->dev,
320 return regmap_update_bits(src4xxx->regmap, reg,
323 dev_info(dai->dev, "not setting up MCLK as not master\n");
344 .id = SRC4XXX_PORTA,
345 .name = "src4xxx-portA",
363 .id = SRC4XXX_PORTB,
364 .name = "src4xxx-portB",
426 return -ENOMEM;
428 src4xxx->regmap = regmap;
429 src4xxx->dev = dev;
430 src4xxx->mclk_hz = 0; /* mclk has not been configured yet */
442 ret = regmap_update_bits(src4xxx->regmap, SRC4XXX_PWR_RST_01,
447 /* set receiver to use master clock (rcv mclk is most likely jittery) */
448 ret = regmap_update_bits(src4xxx->regmap, SRC4XXX_RCV_CTL_0D,
452 "Failed to enable mclk as the PLL1 DIR reference : %d\n", ret);
455 ret = regmap_update_bits(src4xxx->regmap, SRC4XXX_RCV_CTL_0E,
459 dev_err(dev, "Failed to enable mclk rec and div : %d\n", ret);