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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddra74x.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
16 compatible = "arm,cortex-a15";
18 operating-points-v2 = <&cpu0_opp_table>;
21 clock-names = "cpu";
23 clock-latency = <300000>; /* From omap-cpufreq driver */
26 #cooling-cells = <2>; /* min followed by max */
28 vbb-supply = <&abb_mpu>;
40 compatible = "arm,cortex-a15-pmu";
41 interrupt-parent = <&wakeupgen>;
[all …]
H A Ddra72x.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
20 compatible = "arm,cortex-a15-pmu";
21 interrupt-parent = <&wakeupgen>;
27 target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
28 compatible = "ti,sysc-omap4", "ti,sysc";
31 reg-names = "rev", "sysc";
32 ti,sysc-midle = <SYSC_IDLE_FORCE>,
34 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
37 clock-names = "fck";
[all …]
H A Domap2420.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
15 compatible = "ti,omap2-l4", "simple-bus";
16 #address-cells = <1>;
17 #size-cells = <1>;
21 compatible = "ti,omap2-prcm";
25 #address-cells = <1>;
26 #size-cells = <0>;
34 compatible = "ti,omap2-scm", "simple-bus";
36 #address-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-j721s2-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
[all …]
H A Dk3-j784s4-j742s2-main-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/mux/mux.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-ti.h>
12 #include "k3-serdes.h"
15 serdes_refclk: clock-serdes {
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
29 compatible = "mmio-sram";
[all …]
H A Dk3-j721e-beagleboneai64.dts1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * https://beagleboard.org/ai-64
4 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
5 * Copyright (C) 2022-2024 Jason Kridner, BeagleBoard.org Foundation
6 * Copyright (C) 2022-2024 Robert Nelson, BeagleBoard.org Foundation
9 /dts-v1/;
11 #include "k3-j721e.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/leds/common.h>
[all …]
H A Dk3-am69-sk.dts1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
9 /dts-v1/;
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include "k3-j784s4.dtsi"
16 compatible = "ti,am69-sk", "ti,j784s4";
20 stdout-path = "serial2:115200n8";
36 bootph-all;
42 reserved_memory: reserved-memory {
[all …]
H A Dk3-j784s4-j742s2-evm-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
9 #include <dt-bindings/phy/phy-cadence.h>
13 stdout-path = "serial2:115200n8";
28 reserved_memory: reserved-memory {
29 #address-cells = <2>;
30 #size-cells = <2>;
35 no-map;
38 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
39 compatible = "shared-dma-pool";
[all …]
H A Dk3-am68-phycore-som.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
6 * https://www.phytec.eu/en/produkte/system-on-modules/phycore-am68x-tda4x/
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include "k3-j721s2.dtsi"
16 compatible = "phytec,am68-phycore-som", "ti,j721s2";
17 model = "PHYTEC phyCORE-AM68x";
30 bootph-all;
33 reserved_memory: reserved-memory {
[all …]
H A Dk3-j7200-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
9 serdes_refclk: serdes-refclk {
10 #clock-cells = <0>;
11 compatible = "fixed-clock";
17 compatible = "mmio-sram";
19 #address-cells = <1>;
20 #size-cells = <1>;
23 atf-sram@0 {
28 scm_conf: scm-conf@100000 {
[all …]
H A Dk3-am64-phycore-som.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2021-2024 PHYTEC America, LLC - https://www.phytec.com
6 * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH
10 * https://www.phytec.com/product/phycore-am64x
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/leds/common.h>
15 #include <dt-bindings/net/ti-dp83867.h>
18 model = "PHYTEC phyCORE-AM64x";
19 compatible = "phytec,am64-phycore-som", "ti,am642";
30 bootph-all;
[all …]
H A Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
[all …]
H A Dk3-am67a-beagley-ai.dts1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * https://beagley-ai.org/
5 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
9 /dts-v1/;
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include "k3-j722s.dtsi"
16 compatible = "beagle,am67a-beagley-ai", "ti,j722s";
17 model = "BeagleBoard.org BeagleY-AI";
27 stdout-path = &main_uart0;
[all …]
H A Dk3-j721s2-som-p0.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include "k3-j721s2.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
16 bootph-all;
23 reserved_memory: reserved-memory {
24 #address-cells = <2>;
25 #size-cells = <2>;
31 no-map;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/cix/
H A Dsky1.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/cix,sky1.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <2>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a520";
21 enable-method = "psci";
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mailbox/
H A Daltera-mailbox.txt5 - compatible : "altr,mailbox-1.0".
6 - reg : physical base address of the mailbox and length of
8 - #mbox-cells: Common mailbox binding property to identify the number
12 - interrupts : interrupt number. The interrupt specifier format
17 compatible = "altr,mailbox-1.0";
19 interrupt-parent = < &gic_0 >;
21 #mbox-cells = <1>;
25 compatible = "altr,mailbox-1.0";
27 interrupt-parent = < &gic_0 >;
29 #mbox-cells = <1>;
[all …]
H A Dthead,th1520-mbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/thead,th1520-mbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: T-head TH1520 Mailbox Controller
10 The T-head mailbox controller enables communication and coordination between
16 - Michal Wilczynski <m.wilczynski@samsung.com>
20 const: thead,th1520-mbox
24 - description: Clock for the local mailbox
25 - description: Clock for remote ICU 0
[all …]
H A Dgoogle,gs101-mbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/mailbox/google,gs101-mbox.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Tudor Ambarus <tudor.ambarus@linaro.org>
23 const: google,gs101-mbox
31 clock-names:
33 - const: pclk
39 '#mbox-cells':
43 - compatible
[all …]
H A Dsti-mailbox.txt7 ----------
10 - compatible : Should be "st,stih407-mailbox"
11 - reg : Offset and length of the device's register set
12 - mbox-name : Name of the mailbox
13 - #mbox-cells: : Must be 2
20 - interrupts : Contains the IRQ line for a Rx mailbox
25 compatible = "st,stih407-mailbox";
28 #mbox-cells = <2>;
29 mbox-name = "a9";
33 ------
[all …]
H A Dhisilicon,hi6220-mailbox.txt13 --------------------
14 - compatible: Shall be "hisilicon,hi6220-mbox"
15 - reg: Contains the mailbox register address range (base
19 - #mbox-cells: Common mailbox binding property to identify the number
28 - interrupts: Contains the interrupt information for the mailbox
33 --------------------
34 - hi6220,mbox-tx-noirq: Property of MCU firmware's feature, so mailbox driver
40 --------
43 compatible = "hisilicon,hi6220-mbox";
46 interrupt-parent = <&gic>;
[all …]
H A Dti,omap-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
35 lines can also be routed to different processor sub-systems on DRA7xx as they
49 within a SoC. The sub-mailboxes (actual communication channels) are
56 "mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt
59 phandle to the intended sub-mailbox child node to be used for communication.
60 The equivalent "mbox-names" property value can be used to give a name to the
[all …]
H A Domap-mailbox.txt25 routed to different processor sub-systems on DRA7xx as they are routed through
38 a SoC. The sub-mailboxes are represented as child nodes of this parent node.
41 --------------------
42 - compatible: Should be one of the following,
43 "ti,omap2-mailbox" for OMAP2420, OMAP2430 SoCs
44 "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs
45 "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx,
47 "ti,am654-mailbox" for K3 AM65x and J721E SoCs
48 "ti,am64-mailbox" for K3 AM64x SoCs
49 - reg: Contains the mailbox register address range (base
[all …]
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Damphion,vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ming Qian <ming.qian@nxp.com>
11 - Shijie Qin <shijie.qin@nxp.com>
13 description: |-
19 pattern: "^vpu@[0-9a-f]+$"
23 - enum:
24 - nxp,imx8qm-vpu
25 - nxp,imx8qxp-vpu
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8-ss-vpu.dtsi1 // SPDX-License-Identifier: GPL-2.0+
8 #address-cells = <1>;
9 #size-cells = <1>;
12 power-domains = <&pd IMX_SC_R_VPU>;
16 compatible = "fsl,imx6sx-mu";
19 #mbox-cells = <2>;
20 power-domains = <&pd IMX_SC_R_VPU_MU_0>;
25 compatible = "fsl,imx6sx-mu";
28 #mbox-cells = <2>;
29 power-domains = <&pd IMX_SC_R_VPU_MU_1>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/dsp/
H A Dfsl,dsp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daniel Baluta <daniel.baluta@nxp.com>
11 - Shengjiu Wang <shengjiu.wang@nxp.com>
15 advanced pre- and post- audio processing.
20 - fsl,imx8qxp-dsp
21 - fsl,imx8qm-dsp
22 - fsl,imx8mp-dsp
23 - fsl,imx8ulp-dsp
[all …]

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