| /freebsd/sys/contrib/device-tree/Bindings/iio/adc/ |
| H A D | st,stm32-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 STM32 ADC is a successive approximation analog-to-digital converter.
13 stored in a left-aligned or right-aligned 32-bit data register.
17 voltage goes beyond the user-defined, higher or lower thresholds.
22 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
27 - st,stm32f4-adc-core
28 - st,stm32h7-adc-core
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| /freebsd/sys/contrib/device-tree/Bindings/iio/imu/ |
| H A D | adi,adis16480.txt | 6 - compatible: Must be one of
12 * "adi,adis16495-1"
13 * "adi,adis16495-2"
14 * "adi,adis16495-3"
15 * "adi,adis16497-1"
16 * "adi,adis16497-2"
17 * "adi,adis16497-3"
18 - reg: SPI chip select number for the device
19 - spi-max-frequency: Max SPI frequency to use
20 see: Documentation/devicetree/bindings/spi/spi-bus.txt
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| H A D | adi,adis16480.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <alexandru.tachici@analog.com>
15 - adi,adis16375
16 - adi,adis16480
17 - adi,adis16485
18 - adi,adis16488
19 - adi,adis16490
20 - adi,adis16495-1
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| /freebsd/sys/contrib/device-tree/src/arm64/rockchip/ |
| H A D | rk3399-gru-chromebook.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-Chromebook shared properties
8 #include "rk3399-gru.dtsi"
11 pp900_ap: pp900-ap {
12 compatible = "regulator-fixed";
13 regulator-name = "pp900_ap";
16 regulator-always-o
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| H A D | rk3399-gru.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
9 #include "rk3399-op1.dtsi"
18 stdout-path = "serial2:115200n8";
27 * - Rails that only connect to the EC (or devices that the EC talks to)
29 * - Rails _are_ included if the rails go to the AP even if the AP
38 * - The EC controls the enable and the EC always enables a rail as
40 * - The rails are actually connected to each other by a jumper and
45 ppvar_sys: ppvar-sys {
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| /freebsd/sys/contrib/device-tree/src/arm/amlogic/ |
| H A D | meson8.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
7 #include <dt-bindings/clock/meson8b-clkc.h>
8 #include <dt-bindings/gpio/meson8-gpio.h>
9 #include <dt-bindings/power/meson8-power.h>
10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/thermal/thermal.h>
20 #address-cells = <1>;
21 #size-cells = <0>;
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| H A D | meson8b.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 #include <dt-bindings/clock/meson8-ddr-clkc.h>
8 #include <dt-bindings/clock/meson8b-clkc.h>
9 #include <dt-bindings/gpio/meson8b-gpio.h>
10 #include <dt-bindings/power/meson8-power.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
13 #include <dt-bindings/thermal/thermal.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
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| /freebsd/sys/contrib/device-tree/src/arm/samsung/ |
| H A D | exynos5422-odroid-core.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source
6 * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd.
10 #include <dt-bindings/clock/samsung,s2mps11.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
14 #include "exynos5422-cpus.dtsi"
27 stdout-path = "serial2:115200n8";
31 compatible = "samsung,secure-firmware";
35 fixed-rate-clocks {
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| /freebsd/sys/contrib/device-tree/src/arm64/xilinx/ |
| H A D | zynqmp-sm-k26-revA.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for Xilinx ZynqMP SM-K26 rev2/1/B/A
5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
6 * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/phy/phy.h>
18 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
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| /freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
| H A D | dm814x-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #clock-cells = <1>;
11 compatible = "ti,dm814-adpll-s-clock";
14 clock-names = "clkinp", "clkinpulow", "clkinphif";
15 clock-output-names = "481c5040.adpll.dcoclkldo",
22 #clock-cells = <1>;
23 compatible = "ti,dm814-adpll-lj-clock";
26 clock-names = "clkinp", "clkinpulow";
27 clock-output-names = "481c5080.adpll.dcoclkldo",
33 #clock-cells = <1>;
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| /freebsd/sys/dev/spibus/controller/allwinner/ |
| H A D | aw_spi.c | 1 /*-
43 #include <dev/clk/clk.h>
108 #define AW_SPI_CCR 0x24 /* Clock Rate Control Register */
126 { "allwinner,sun8i-h3-spi", 1 },
133 { -1, 0 }
156 #define AW_SPI_LOCK(sc) mtx_lock(&(sc)->mtx)
157 #define AW_SPI_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
158 #define AW_SPI_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
159 #define AW_SPI_READ_1(sc, reg) bus_read_1((sc)->res[0], (reg))
160 #define AW_SPI_WRITE_1(sc, reg, val) bus_write_1((sc)->res[0], (reg), (val))
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| /freebsd/sys/contrib/device-tree/src/arm64/freescale/ |
| H A D | imx8mp.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/power/imx8mp-power.h>
8 #include <dt-bindings/reset/imx8mp-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interconnect/fsl,imx8mp.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
15 #include "imx8mp-pinfunc.h"
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| /freebsd/sys/dev/flash/flexspi/ |
| H A D | flex_spi.c | 1 /*-
45 #include <dev/clk/clk.h>
66 {"nxp,lx2160a-fspi", true},
136 return ((bus_read_4(sc->mem_res, offset))); in read_reg()
143 bus_write_4(sc->mem_res, offset, (value)); in write_reg()
164 } while (condition && (--iterations > 0)); in reg_read_poll_tout()
170 flex_spi_clk_setup(struct flex_spi_softc *sc, uint32_t rate) in flex_spi_clk_setup() argument
175 ret |= clk_disable(sc->fspi_clk_en); in flex_spi_clk_setup()
176 ret |= clk_disable(sc->fspi_clk); in flex_spi_clk_setup()
178 ret |= clk_set_freq(sc->fspi_clk, rate, 0); in flex_spi_clk_setup()
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| /freebsd/sys/dev/cxgbe/common/ |
| H A D | t4_hw.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
44 pause("t4hw", (x) * hz / 1000); \
48 * t4_wait_op_done_val - wait until an operation is completed
51 * @mask: a single-bit field within @reg that indicates completion
60 * operation completes and -EAGAIN otherwise.
73 if (- in t4_wait_op_done_val()
6444 unsigned int clk = adap->params.vpd.cclk * 1000; t4_set_sched_bps() local
10216 t4_idma_monitor(struct adapter * adapter,struct sge_idma_monitor_state * idma,int hz,int ticks) t4_idma_monitor() argument
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| /freebsd/sys/dev/cxgb/common/ |
| H A D | cxgb_t3_hw.c | 2 SPDX-License-Identifier: BSD-2-Clause
4 Copyright (c) 2007-2009, Chelsio Inc.
38 * t3_wait_op_done_val - wait until an operation is completed
41 * @mask: a single-bit field within @reg that indicates completion
50 * operation completes and -EAGAIN otherwise.
63 if (--attempts == 0) in t3_wait_op_done_val()
64 return -EAGAIN; in t3_wait_op_done_val()
71 * t3_write_regs - write a bunch of registers
84 while (n--) { in t3_write_regs()
85 t3_write_reg(adapter, p->reg_addr + offset, p->val); in t3_write_regs()
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| /freebsd/contrib/ntp/ntpd/ |
| H A D | refclock_arc.c | 2 * refclock_arc - clock driver for ARCRON MSF/DCF/WWVB receivers
35 Modifications by Damon Hart-Davis, <d@hd.org>, 1997.
37 Modifications by Christopher Price, <cprice@cs-home.com>, 2003.
44 Orginally developed and used with ntp3-5.85 by Derek Mulcahy.
46 Built against ntp3-5.90 on Solaris 2.5 using gcc 2.7.2.
52 -----
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| /freebsd/sys/dev/sfxge/common/ |
| H A D | efx_regs_mcdi.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright 2008-2013 Solarflare Communications Inc. All rights reserved.
32 /* Power-on reset state */
54 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
57 /* The rest of these are firmware-defined */
65 /* Values to be written to the per-port status dword in shared
94 * | | \--- Response
95 * | \------- Error
96 * \------------------------------ Resync (always set)
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| /freebsd/sys/dev/qlnx/qlnxe/ |
| H A D | reg_addr.h | 2 * Copyright (c) 2017-2018 Cavium, Inc.
78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
116 … (0x1<<9) // Fast back-to-back transaction ena…
128 … (0x1<<23) // Fast back-to-back capable. Not ap…
145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
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| /freebsd/sys/dev/sym/ |
| H A D | sym_hipd.c | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
5 * PCI-SCSI controllers.
7 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr>
9 * This driver also supports the following Symbios/LSI PCI-SCSI chips:
14 * This driver for FreeBSD-CAM is derived from the Linux sym53c8xx driver.
15 * Copyright (C) 1998-1999 Gerard Roudier
18 * a port of the FreeBSD ncr driver to Linux-1.2.13.
22 * Stefan Esser <se@mi.Uni-Koeln.de>
26 * FreeBSD-CAM services is based on the aic7xxx driver for FreeBSD-CAM
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| /freebsd/sys/dev/bxe/ |
| H A D | bxe_elink.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
508 /* When this pin is active high during reset, 10GBASE-T core is power
509 * down, When it is active low the 10GBASE-T is power up
774 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
778 /* LED Blink rate that will achieve ~15.9Hz */
936 (_phy)->def_md_devad, \
942 (_phy)->def_md_devad, \
970 * elink_check_lfa - This function checks if link reinitialization is required,
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