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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dmediatek-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek-dwma
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H A Dsnps,dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare MAC
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.40a
25 - snps,dwmac-3.50a
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H A Dbrcm,bcmgenet.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Doug Berger <opendmb@gmail.com>
11 - Florian Fainelli <f.fainelli@gmail.com>
16 - brcm,genet-v1
17 - brcm,genet-v2
18 - brcm,genet-v3
19 - brcm,genet-v4
20 - brcm,genet-v5
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H A Dbrcm,bcmgenet.txt4 - compatible: should contain one of "brcm,genet-v1", "brcm,genet-v2",
5 "brcm,genet-v3", "brcm,genet-v4", "brcm,genet-v5", "brcm,bcm2711-genet-v5" or
6 "brcm,bcm7712-genet-v5".
7 - reg: address and length of the register set for the device
8 - interrupts and/or interrupts-extended: must be two cells, the first cell
11 optional third interrupt cell for Wake-on-LAN can be specified.
12 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
14 - phy-mode: see ethernet.txt file in the same directory
15 - #address-cells: should be 1
16 - #size-cells: should be 1
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H A Dibm,emac.txt8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
22 - local-mac-address : 6 bytes, MAC address
23 - mal-device : phandle of the associated McMAL node
24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
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/freebsd/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
61 /* *INDENT-OFF* */
65 /* *INDENT-ON* */
97 #define AL_ETH_TSO_MSS_MAX_VAL (AL_ETH_MAX_FRAME_LEN - 200)
130 /** MAC media mode */
136 AL_ETH_MAC_MODE_10G_SGMII, /**< SGMII using the 10G MAC, don't use*/
137 AL_ETH_MAC_MODE_XLG_LL_40G, /**< applies to 40G mode using the 40G low latency (LL) MAC */
138 AL_ETH_MAC_MODE_KR_LL_25G, /**< applies to 25G mode using the 10/25G low latency (LL) MAC */
139 AL_ETH_MAC_MODE_XLG_LL_50G, /**< applies to 50G mode using the 40/50G low latency (LL) MAC */
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H A Dal_hal_eth_ec_regs.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
77 /* [0x0] General configuration of the MAC side of the Ethern ... */
190 /* [0x8] MAC Hash configuration */
192 /* [0xc] MAC Hash configuration */
194 /* [0x10] MAC Hash configuration */
206 /* [0x28] MAC hash table address */
208 /* [0x2c] MAC hash table data */
214 /* [0x38] VLAN p-bits table address */
216 /* [0x3c] VLAN p-bits table data */
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H A Dal_hal_eth_main.c1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
98 /* tx Meta Descriptor defines - MacSec */
105 #define AL_ETH_TX_MACSEC_SECURED_PYLD_LEN_LSB_SHIFT 10 /* Secure Payload Length (0x3FFF for non-S…
364 al_warn("[%s] warn: failed to change state, error %d\n", dma->name, rc); in al_udma_state_set_wait()
376 if (count-- == 0) { in al_udma_state_set_wait()
378 dma->name, al_udma_states_name[new_state]); in al_udma_state_set_wait()
379 return -ETIMEDOUT; in al_udma_state_set_wait()
389 al_reg_write32(&adapter->ec_regs_base->epe_p[idx].comp_data, reg_entry->data); in al_eth_epe_entry_set()
390 al_reg_write32(&adapter->ec_regs_base->epe_p[idx].comp_mask, reg_entry->mask); in al_eth_epe_entry_set()
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/freebsd/sys/dev/vge/
H A Dif_vgereg.h1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
37 * Definitions for the built-in copper PHY can be found in vgphy.h.
41 * using 32-bit I/O cycles, but some of them are less than 32 bits
119 #define VGE_SSTIMER 0x74 /* single-shot timer */
127 #define VGE_RXCFG 0x7E /* MAC RX config */
128 #define VGE_TXCFG 0x7F /* MAC TX config */
148 #define VGE_WOLCFGS 0xA3 /* WOL config set */
152 #define VGE_WOLCFGC 0xA7 /* WOL config clear */
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H A Dif_vge.c1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
46 * combines a tri-speed ethernet MAC and PHY, with the following
54 * o 64-bit multicast hash table filter
66 * receive data buffers must be aligned on a 32-bit boundary. This is
67 * not a problem where the VT6122 is used as a LOM device in x86-based
71 * The other issue has to do with the way 64-bit addresses are handled.
74 * I/O registers. If you only have a 32-bit system, then this isn't
75 * an issue, but if you have a 64-bit system and more than 4GB of
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/freebsd/sys/dev/msk/
H A Dif_mskreg.h17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
65 * 4. Neither the name of the author nor the names of any co-contributors
82 /*-
110 * D-Link PCI vendor ID
154 * D-Link gigabit ethernet device ID
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/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dakebono.dts12 /dts-v1/;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <1600000000>; // 1.6 GHz
36 timebase-frequency = <100000000>; // 100Mhz
37 i-cache-line-size = <32>;
38 d-cache-line-size = <32>;
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/freebsd/sys/dev/e1000/
H A Dif_em.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2001-2024, Intel Corporation
40 static const char em_driver_version[] = "7.7.8-fbsd";
41 static const char igb_driver_version[] = "2.5.28-fbsd";
55 /* Intel(R) - lem-class legacy devices */
136 /* Intel(R) - em-class devices */
185 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"),
189 "Intel(R) 82566DM-2 ICH9 AMT"),
190 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"),
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H A Dif_em.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2001-2024, Intel Corporation
104 * Valid Range: 80-256 for 82542 and 82543-based adapters
105 * 80-4096 for others
121 * EM_MAX_RXD - Maximum number of receive Descriptors
122 * Valid Range: 80-256 for 82542 and 82543-based adapters
123 * 80-4096 for others
140 * EM_TIDV - Transmit Interrupt Delay Value
141 * Valid Range: 0-65535 (0=off)
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/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_mcp.c2 * Copyright (c) 2017-2018 Cavium, Inc.
57 ecore_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
61 ecore_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
89 if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base) in ecore_mcp_is_init()
97 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, in ecore_mcp_cmd_port_init()
101 p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize, in ecore_mcp_cmd_port_init()
105 p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn)); in ecore_mcp_cmd_port_init()
111 u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length); in ecore_mcp_read_mb()
116 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev)) in ecore_mcp_read_mb()
120 if (!p_hwfn->mcp_info->public_base) in ecore_mcp_read_mb()
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H A Decore_mcp_api.h2 * Copyright (c) 2017-2018 Cavium, Inc.
133 u8 mac[ETH_ALEN]; member
154 u8 name[MCP_DRV_VER_STR_SIZE - 4];
281 /* First entry for primary MAC, 2 secondary MACs possible */
282 u8 mac[ECORE_MFW_TLV_MAC_COUNT][6]; member
576 * @brief - returns the link params of the hw function
586 * @brief - return the link state of the hw function
596 * @brief - return the link capabilities of the hw function
610 * @param b_up - raise link if `true'. Reset link if `false'.
623 * @param p_mfw_ver - mfw version value
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/freebsd/sbin/ifconfig/
H A Difconfig.81 .\"-
2 .\" SPDX-License-Identifier: BSD-3-Clause
93 .Bl -tag -width indent
120 The format is specified as a comma-separated list of
141 .Bl -tag -width default
145 .Bl -tag -width default -compact
158 Adjust the display of link-level ethernet (MAC) addresses:
160 .Bl -tag -width default -compact
175 .Bl -tag -width default -compact
192 .Bl -tag -width default -compact
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/freebsd/sys/dev/qcom_ess_edma/
H A Dqcom_ess_edma_reg.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
5 * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
32 * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
138 #define EDMA_REG_TXF_WATER_MARK 0x408 /* In 8-bytes */
269 #define EDMA_RFS_FLOW_ENTRIES_MASK (EDMA_RFS_FLOW_ENTRIES - 1)
316 /* WoL Pattern Length Register */
329 /* WoL Control Register */
341 /* MAC Control Register */
345 /* WoL Pattern Register */
[all …]
H A Dqcom_ess_edma_hw.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
66 * for the ESS core - and that includes both the EDMA (ethernet)
69 * AND, it's a placeholder for what the linux ess-edma driver
72 * ess-switch won't be initialised. In that case it defaults
77 * So, for now this is a big no-op, at least until everything
79 * this EDMA driver code to co-exist.
87 device_printf(sc->sc_dev, "%s: called, TODO!\n", __func__); in qcom_ess_edma_hw_reset()
90 * This is where the linux ess-edma driver would reset the in qcom_ess_edma_hw_reset()
95 * and here's where the linux ess-edma driver would program in qcom_ess_edma_hw_reset()
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/freebsd/sys/dev/igc/
H A Dif_igc.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2001-2024, Intel Corporation
6 * Copyright (c) 2021-2024 Rubicon Communications, LLC (Netgate)
51 /* Intel(R) PRO/1000 Network Connection - igc */
53 "Intel(R) Ethernet Controller I225-LM"),
55 "Intel(R) Ethernet Controller I225-V"),
57 "Intel(R) Ethernet Controller I225-K"),
59 "Intel(R) Ethernet Controller I225-IT"),
61 "Intel(R) Ethernet Controller I220-V"),
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/freebsd/sys/dev/cxgbe/common/
H A Dt4_hw.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
39 MAX_MTU = 9600, /* max MAC MTU, excluding header + FCS */
57 NWOL_PAT = 8, /* # of WoL patterns */
58 WOL_PAT_LEN = 128, /* length of WoL patterns */
69 CIMLA_SIZE = 256 * 8, /* 256 rows * ceil(235/32) 32-bit words */
70 CIMLA_SIZE_T6 = 256 * 10, /* 256 rows * ceil(311/32) 32-bit words */
71 CIM_PIFLA_SIZE = 64, /* # of 192-bit words in CIM PIF LA */
72 CIM_MALA_SIZE = 64, /* # of 160-bit words in CIM MA LA */
73 CIM_IBQ_SIZE = 128, /* # of 128-bit words in a CIM IBQ */
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/freebsd/share/man/man4/
H A Dfxp.436 .Bd -ragged -offset indent
44 .Bd -literal -offset indent
57 Wake On Lan (WOL) support is provided on all controllers
63 .Bl -tag -width "10baseT/UTP"
77 .Bl -tag -width "full-duplex"
78 .It Cm full-duplex
80 .It Cm half-duplex
104 .Bl -tag -width link0
120 .Bl -bullet -compact
136 Intel PRO/100 S Desktop, Server and Dual-Port Server Adapters
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/freebsd/share/misc/
H A Diso6392 # ISO 639-2 language codes
4 # From http://www.loc.gov/standards/iso639-2/ :
6 # The Library of Congress has been designated the ISO 639-2/RA for the
7 # purpose of processing requests for alpha-3 language codes comprising the
9 # languages -- Part 2: alpha-3 code. The ISO 639-2/RA receives and reviews
16 # This is the official site of the ISO 639-2 Registration Authority and thus
18 # 639-2 please contact us at:
22 # Washington, DC 20540-4402
23 # E-mail: iso639-2@loc.gov
30 # Download the file http://www.loc.gov/standards/iso639-2/ISO-639-2_utf-8.txt
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/freebsd/sys/dev/ae/
H A Dif_ae.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
91 { -1, 0, 0 }
95 { -1, 0, 0 }
99 { -1, 0, 0 }
189 bus_read_4((sc)->mem[0], (reg))
191 bus_read_2((sc)->mem[0], (reg))
193 bus_read_1((sc)->mem[0], (reg))
195 bus_write_4((sc)->mem[0], (reg), (val))
197 bus_write_2((sc)->mem[0], (reg), (val))
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/freebsd/sys/dev/et/
H A Dif_et.c1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
187 nitems(et_devices) - 1);
209 for (d = et_devices; d->desc != NULL; ++d) { in et_probe()
210 if (vid == d->vid && did == d->did) { in et_probe()
211 device_set_desc(dev, d->desc); in et_probe()
228 sc->dev = dev; in et_attach()
229 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, in et_attach()
231 callout_init_mtx(&sc->sc_tick, &sc->sc_mtx, 0); in et_attach()
233 ifp = sc->ifp = if_alloc(IFT_ETHER); in et_attach()
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