Lines Matching +full:mac +full:- +full:wol
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2001-2024, Intel Corporation
40 static const char em_driver_version[] = "7.7.8-fbsd";
41 static const char igb_driver_version[] = "2.5.28-fbsd";
55 /* Intel(R) - lem-class legacy devices */
136 /* Intel(R) - em-class devices */
185 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"),
189 "Intel(R) 82566DM-2 ICH9 AMT"),
190 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"),
193 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"),
194 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"),
195 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"),
196 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"),
198 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"),
199 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"),
200 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"),
201 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"),
202 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"),
203 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"),
204 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"),
211 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"),
212 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"),
214 "Intel(R) I218-LM LPTLP"),
215 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"),
216 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"),
217 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"),
218 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"),
219 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"),
220 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"),
221 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"),
223 "Intel(R) I219-LM SPT-H(2)"),
225 "Intel(R) I219-V SPT-H(2)"),
227 "Intel(R) I219-LM LBG(3)"),
229 "Intel(R) I219-LM SPT(4)"),
230 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"),
232 "Intel(R) I219-LM SPT(5)"),
233 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"),
235 "Intel(R) I219-LM CNP(6)"),
236 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"),
238 "Intel(R) I219-LM CNP(7)"),
239 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"),
241 "Intel(R) I219-LM ICP(8)"),
242 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"),
244 "Intel(R) I219-LM ICP(9)"),
245 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"),
247 "Intel(R) I219-LM CMP(10)"),
249 "Intel(R) I219-V CMP(10)"),
251 "Intel(R) I219-LM CMP(11)"),
253 "Intel(R) I219-V CMP(11)"),
255 "Intel(R) I219-LM CMP(12)"),
257 "Intel(R) I219-V CMP(12)"),
259 "Intel(R) I219-LM TGP(13)"),
261 "Intel(R) I219-V TGP(13)"),
263 "Intel(R) I219-LM TGP(14)"),
265 "Intel(R) I219-V GTP(14)"),
267 "Intel(R) I219-LM TGP(15)"),
269 "Intel(R) I219-V TGP(15)"),
271 "Intel(R) I219-LM ADL(16)"),
273 "Intel(R) I219-V ADL(16)"),
275 "Intel(R) I219-LM ADL(17)"),
277 "Intel(R) I219-V ADL(17)"),
279 "Intel(R) I219-LM MTP(18)"),
281 "Intel(R) I219-V MTP(18)"),
283 "Intel(R) I219-LM ADL(19)"),
285 "Intel(R) I219-V ADL(19)"),
287 "Intel(R) I219-LM LNL(20)"),
289 "Intel(R) I219-V LNL(20)"),
291 "Intel(R) I219-LM LNL(21)"),
293 "Intel(R) I219-V LNL(21)"),
295 "Intel(R) I219-LM RPL(22)"),
297 "Intel(R) I219-V RPL(22)"),
299 "Intel(R) I219-LM RPL(23)"),
301 "Intel(R) I219-V RPL(23)"),
303 "Intel(R) I219-LM ARL(24)"),
305 "Intel(R) I219-V ARL(24)"),
307 "Intel(R) I219-LM PTP(25)"),
309 "Intel(R) I219-V PTP(25)"),
311 "Intel(R) I219-LM PTP(26)"),
313 "Intel(R) I219-V PTP(26)"),
315 "Intel(R) I219-LM PTP(27)"),
317 "Intel(R) I219-V PTP(27)"),
324 /* Intel(R) - igb-class devices */
354 "Intel(R) I340-T2 82580 (Dual Copper)"),
356 "Intel(R) I340-F4 82580 (Quad Fiber)"),
360 "Intel(R) I347-AT4 DH89XXCC"),
469 /* Management and WOL Support */
481 /* MSI-X handlers */
677 /* Energy efficient ethernet - default to OFF */
698 /* Global used in WOL setup with multiport cards */
771 struct e1000_hw *hw = &sc->hw; in em_get_regs()
851 if_softc_ctx_t scctx = sc->shared; in em_get_regs()
852 struct rx_ring *rxr = &rx_que->rxr; in em_get_regs()
853 struct tx_ring *txr = &tx_que->txr; in em_get_regs()
854 int ntxd = scctx->isc_ntxd[0]; in em_get_regs()
855 int nrxd = scctx->isc_nrxd[0]; in em_get_regs()
859 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); in em_get_regs()
860 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); in em_get_regs()
863 j, rxr->rx_base[j].read.buffer_addr, staterr, length); in em_get_regs()
867 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; in em_get_regs()
872 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, in em_get_regs()
873 buf->eop != -1 ? in em_get_regs()
874 txr->tx_base[buf->eop].upper.fields.status & in em_get_regs()
905 switch (sc->hw.mac.type) { in em_set_num_queues()
969 sc->ctx = sc->osdep.ctx = ctx; in em_if_attach_pre()
970 sc->dev = sc->osdep.dev = dev; in em_if_attach_pre()
971 scctx = sc->shared = iflib_get_softc_ctx(ctx); in em_if_attach_pre()
972 sc->media = iflib_get_media(ctx); in em_if_attach_pre()
973 hw = &sc->hw; in em_if_attach_pre()
975 /* Determine hardware and mac info */ in em_if_attach_pre()
986 sc->enable_aim = em_enable_aim; in em_if_attach_pre()
988 CTLFLAG_RW, &sc->enable_aim, 0, in em_if_attach_pre()
1012 if (hw->mac.type >= e1000_i350) { in em_if_attach_pre()
1036 scctx->isc_tx_nsegments = EM_MAX_SCATTER; in em_if_attach_pre()
1037 scctx->isc_nrxqsets_max = in em_if_attach_pre()
1038 scctx->isc_ntxqsets_max = em_set_num_queues(ctx); in em_if_attach_pre()
1041 scctx->isc_ntxqsets_max); in em_if_attach_pre()
1043 if (hw->mac.type >= igb_mac_min) { in em_if_attach_pre()
1044 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * in em_if_attach_pre()
1046 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * in em_if_attach_pre()
1048 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); in em_if_attach_pre()
1049 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); in em_if_attach_pre()
1050 scctx->isc_txrx = &igb_txrx; in em_if_attach_pre()
1051 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; in em_if_attach_pre()
1052 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; in em_if_attach_pre()
1053 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; in em_if_attach_pre()
1054 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; in em_if_attach_pre()
1055 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | in em_if_attach_pre()
1057 if (hw->mac.type != e1000_82575) in em_if_attach_pre()
1058 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; in em_if_attach_pre()
1064 scctx->isc_msix_bar = pci_msix_table_bar(dev); in em_if_attach_pre()
1065 } else if (hw->mac.type >= em_mac_min) { in em_if_attach_pre()
1066 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * in em_if_attach_pre()
1068 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * in em_if_attach_pre()
1070 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); in em_if_attach_pre()
1071 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); in em_if_attach_pre()
1072 scctx->isc_txrx = &em_txrx; in em_if_attach_pre()
1073 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; in em_if_attach_pre()
1074 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; in em_if_attach_pre()
1075 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; in em_if_attach_pre()
1076 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; in em_if_attach_pre()
1077 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | in em_if_attach_pre()
1081 scctx->isc_capenable &= ~IFCAP_TSO; in em_if_attach_pre()
1086 * i218-i219 Specification Update 1.5.4.5 in em_if_attach_pre()
1088 if (hw->mac.type == e1000_pch_spt) in em_if_attach_pre()
1089 scctx->isc_capenable &= ~IFCAP_TSO; in em_if_attach_pre()
1092 * We support MSI-X with 82574 only, but indicate to iflib(4) in em_if_attach_pre()
1095 if (hw->mac.type == e1000_82574) { in em_if_attach_pre()
1096 scctx->isc_msix_bar = pci_msix_table_bar(dev); in em_if_attach_pre()
1098 scctx->isc_msix_bar = -1; in em_if_attach_pre()
1099 scctx->isc_disable_msix = 1; in em_if_attach_pre()
1102 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * in em_if_attach_pre()
1104 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * in em_if_attach_pre()
1106 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); in em_if_attach_pre()
1107 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); in em_if_attach_pre()
1108 scctx->isc_txrx = &lem_txrx; in em_if_attach_pre()
1109 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; in em_if_attach_pre()
1110 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; in em_if_attach_pre()
1111 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; in em_if_attach_pre()
1112 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS; in em_if_attach_pre()
1114 scctx->isc_capabilities |= IFCAP_TSO6; in em_if_attach_pre()
1115 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | in em_if_attach_pre()
1119 scctx->isc_capenable &= ~IFCAP_TSO; in em_if_attach_pre()
1122 if (hw->device_id == E1000_DEV_ID_82541ER || in em_if_attach_pre()
1123 hw->device_id == E1000_DEV_ID_82541ER_LOM) { in em_if_attach_pre()
1124 scctx->isc_capabilities &= ~IFCAP_VLAN_HWTAGGING; in em_if_attach_pre()
1125 scctx->isc_capenable = scctx->isc_capabilities; in em_if_attach_pre()
1128 if (hw->mac.type == e1000_82542) { in em_if_attach_pre()
1129 scctx->isc_capabilities &= ~(IFCAP_HWCSUM | in em_if_attach_pre()
1133 scctx->isc_capenable = scctx->isc_capabilities; in em_if_attach_pre()
1136 if (hw->mac.type < e1000_82544 || in em_if_attach_pre()
1137 hw->mac.type == e1000_82547 || in em_if_attach_pre()
1138 hw->mac.type == e1000_82547_rev_2) { in em_if_attach_pre()
1139 scctx->isc_capabilities &= in em_if_attach_pre()
1141 scctx->isc_capenable = scctx->isc_capabilities; in em_if_attach_pre()
1144 if (hw->mac.type < e1000_82545){ in em_if_attach_pre()
1145 scctx->isc_capabilities &= ~IFCAP_HWCSUM_IPV6; in em_if_attach_pre()
1146 scctx->isc_capenable = scctx->isc_capabilities; in em_if_attach_pre()
1149 * "PCI/PCI-X SDM 4.0" page 33 (b): in em_if_attach_pre()
1152 if (hw->mac.type == e1000_82547 || in em_if_attach_pre()
1153 hw->mac.type == e1000_82547_rev_2) in em_if_attach_pre()
1154 scctx->isc_capenable &= ~(IFCAP_HWCSUM | in em_if_attach_pre()
1158 scctx->isc_msix_bar = 0; in em_if_attach_pre()
1171 ** must happen after the MAC is in em_if_attach_pre()
1174 if ((hw->mac.type == e1000_ich8lan) || in em_if_attach_pre()
1175 (hw->mac.type == e1000_ich9lan) || in em_if_attach_pre()
1176 (hw->mac.type == e1000_ich10lan) || in em_if_attach_pre()
1177 (hw->mac.type == e1000_pchlan) || in em_if_attach_pre()
1178 (hw->mac.type == e1000_pch2lan) || in em_if_attach_pre()
1179 (hw->mac.type == e1000_pch_lpt)) { in em_if_attach_pre()
1181 sc->flash = bus_alloc_resource_any(dev, in em_if_attach_pre()
1183 if (sc->flash == NULL) { in em_if_attach_pre()
1189 hw->flash_address = (u8 *)sc->flash; in em_if_attach_pre()
1190 sc->osdep.flash_bus_space_tag = in em_if_attach_pre()
1191 rman_get_bustag(sc->flash); in em_if_attach_pre()
1192 sc->osdep.flash_bus_space_handle = in em_if_attach_pre()
1193 rman_get_bushandle(sc->flash); in em_if_attach_pre()
1201 else if (hw->mac.type >= e1000_pch_spt) { in em_if_attach_pre()
1202 sc->osdep.flash_bus_space_tag = sc->osdep.mem_bus_space_tag; in em_if_attach_pre()
1203 sc->osdep.flash_bus_space_handle = in em_if_attach_pre()
1204 sc->osdep.mem_bus_space_handle + E1000_FLASH_BASE_ADDR; in em_if_attach_pre()
1220 if (hw->mac.type < igb_mac_min) { in em_if_attach_pre()
1222 "receive interrupt delay in usecs", &sc->rx_int_delay, in em_if_attach_pre()
1225 "transmit interrupt delay in usecs", &sc->tx_int_delay, in em_if_attach_pre()
1228 if (hw->mac.type >= e1000_82540 && hw->mac.type < igb_mac_min) { in em_if_attach_pre()
1231 &sc->rx_abs_int_delay, in em_if_attach_pre()
1235 &sc->tx_abs_int_delay, in em_if_attach_pre()
1239 hw->mac.autoneg = DO_AUTO_NEG; in em_if_attach_pre()
1240 hw->phy.autoneg_wait_to_complete = false; in em_if_attach_pre()
1241 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; in em_if_attach_pre()
1243 if (hw->mac.type < em_mac_min) { in em_if_attach_pre()
1248 if (hw->phy.media_type == e1000_media_type_copper) { in em_if_attach_pre()
1249 hw->phy.mdix = AUTO_ALL_MODES; in em_if_attach_pre()
1250 hw->phy.disable_polarity_correction = false; in em_if_attach_pre()
1251 hw->phy.ms_type = EM_MASTER_SLAVE; in em_if_attach_pre()
1258 scctx->isc_max_frame_size = hw->mac.max_frame_size = in em_if_attach_pre()
1265 hw->mac.report_tx_early = 1; in em_if_attach_pre()
1268 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * in em_if_attach_pre()
1270 if (sc->mta == NULL) { in em_if_attach_pre()
1278 sc->tso_automasked = 0; in em_if_attach_pre()
1286 if (hw->mac.type < igb_mac_min) in em_if_attach_pre()
1287 hw->dev_spec.ich8lan.eee_disable = eee_setting; in em_if_attach_pre()
1289 hw->dev_spec._82575.eee_disable = eee_setting; in em_if_attach_pre()
1297 ** mac from that. in em_if_attach_pre()
1304 ** Some PCI-E parts fail the first check due to in em_if_attach_pre()
1316 /* Copy the permanent MAC address out of the EEPROM */ in em_if_attach_pre()
1319 "EEPROM read error while reading MAC address\n"); in em_if_attach_pre()
1324 if (!em_is_valid_ether_addr(hw->mac.addr)) { in em_if_attach_pre()
1325 if (sc->vf_ifp) { in em_if_attach_pre()
1327 (struct ether_addr *)hw->mac.addr); in em_if_attach_pre()
1329 device_printf(dev, "Invalid MAC address\n"); in em_if_attach_pre()
1341 * Get Wake-on-Lan and Management info for later use in em_if_attach_pre()
1345 /* Enable only WOL MAGIC by default */ in em_if_attach_pre()
1346 scctx->isc_capenable &= ~IFCAP_WOL; in em_if_attach_pre()
1347 if (sc->wol != 0) in em_if_attach_pre()
1348 scctx->isc_capenable |= IFCAP_WOL_MAGIC; in em_if_attach_pre()
1350 iflib_set_mac(ctx, hw->mac.addr); in em_if_attach_pre()
1358 free(sc->mta, M_DEVBUF); in em_if_attach_pre()
1367 struct e1000_hw *hw = &sc->hw; in em_if_attach_post()
1373 device_printf(sc->dev, "Interface setup failed: %d\n", error); in em_if_attach_post()
1381 hw->mac.get_link_status = 1; in em_if_attach_post()
1385 /* Non-AMT based hardware can now take control from firmware */ in em_if_attach_post()
1386 if (sc->has_manage && !sc->has_amt) in em_if_attach_post()
1417 e1000_phy_hw_reset(&sc->hw); in em_if_detach()
1422 free(sc->mta, M_DEVBUF); in em_if_detach()
1423 sc->mta = NULL; in em_if_detach()
1459 if (sc->hw.mac.type == e1000_pch2lan) in em_if_resume()
1460 e1000_resume_workarounds_pchlan(&sc->hw); in em_if_resume()
1476 switch (sc->hw.mac.type) { in em_if_mtu_set()
1504 if (sc->hw.mac.type >= igb_mac_min) in em_if_mtu_set()
1509 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { in em_if_mtu_set()
1513 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = in em_if_mtu_set()
1531 if_softc_ctx_t scctx = sc->shared; in em_if_init()
1538 /* Get the latest mac address, User can use a LAA */ in em_if_init()
1539 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN); in em_if_init()
1542 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); in em_if_init()
1550 if (sc->hw.mac.type == e1000_82571) { in em_if_init()
1551 e1000_set_laa_state_82571(&sc->hw, true); in em_if_init()
1552 e1000_rar_set(&sc->hw, sc->hw.mac.addr, in em_if_init()
1553 E1000_RAR_ENTRIES - 1); in em_if_init()
1560 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; in em_if_init()
1562 struct tx_ring *txr = &tx_que->txr; in em_if_init()
1564 txr->tx_rs_cidx = txr->tx_rs_pidx; in em_if_init()
1568 * off-by-one error when calculating how many descriptors are in em_if_init()
1571 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; in em_if_init()
1575 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); in em_if_init()
1578 if (sc->hw.mac.type >= igb_mac_min) in em_if_init()
1579 e1000_rx_fifo_flush_base(&sc->hw); in em_if_init()
1590 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); in em_if_init()
1598 e1000_clear_hw_cntrs_base_generic(&sc->hw); in em_if_init()
1600 /* MSI-X configuration for 82574 */ in em_if_init()
1601 if (sc->hw.mac.type == e1000_82574) { in em_if_init()
1602 int tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); in em_if_init()
1605 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); in em_if_init()
1606 /* Set the IVAR - interrupt vector routing. */ in em_if_init()
1607 E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars); in em_if_init()
1608 } else if (sc->intr_type == IFLIB_INTR_MSIX) { in em_if_init()
1614 E1000_READ_REG(&sc->hw, E1000_ICR); in em_if_init()
1615 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC); in em_if_init()
1618 if (sc->has_manage && sc->has_amt) in em_if_init()
1622 if (sc->hw.mac.type >= igb_mac_min && in em_if_init()
1623 sc->hw.phy.media_type == e1000_media_type_copper) { in em_if_init()
1624 if (sc->hw.mac.type == e1000_i354) in em_if_init()
1625 e1000_set_eee_i354(&sc->hw, true, true); in em_if_init()
1627 e1000_set_eee_i350(&sc->hw, true, true); in em_if_init()
1646 struct e1000_hw *hw = &sc->hw; in em_newitr()
1652 rxbytes = atomic_load_long(&rxr->rx_bytes); in em_newitr()
1653 txbytes = atomic_load_long(&txr->tx_bytes); in em_newitr()
1661 if (sc->enable_aim) { in em_newitr()
1662 nextlatency = rxr->rx_nextlatency; in em_newitr()
1664 /* Use half default (4K) ITR if sub-gig */ in em_newitr()
1665 if (sc->link_speed != 1000) { in em_newitr()
1670 if (sc->shared->isc_max_frame_size * 2 > (sc->pba << 10)) { in em_newitr()
1672 sc->enable_aim = 0; in em_newitr()
1678 txpackets = atomic_load_long(&txr->tx_packets); in em_newitr()
1684 rxpackets = atomic_load_long(&rxr->rx_packets); in em_newitr()
1729 device_printf(sc->dev, in em_newitr()
1735 if (sc->enable_aim == 1 && nextlatency == itr_latency_lowest) in em_newitr()
1739 rxr->rx_nextlatency = nextlatency; in em_newitr()
1743 rxr->rx_nextlatency = nextlatency; in em_newitr()
1764 if (hw->mac.type >= igb_mac_min) { in em_newitr()
1767 if (hw->mac.type == e1000_82575) in em_newitr()
1772 if (newitr != que->itr_setting) { in em_newitr()
1773 que->itr_setting = newitr; in em_newitr()
1774 E1000_WRITE_REG(hw, E1000_EITR(que->msix), in em_newitr()
1775 que->itr_setting); in em_newitr()
1780 if (newitr != que->itr_setting) { in em_newitr()
1781 que->itr_setting = newitr; in em_newitr()
1782 if (hw->mac.type == e1000_82574 && que->msix) { in em_newitr()
1784 E1000_EITR_82574(que->msix), in em_newitr()
1785 que->itr_setting); in em_newitr()
1788 que->itr_setting); in em_newitr()
1803 struct e1000_hw *hw = &sc->hw; in em_intr()
1804 struct em_rx_queue *que = &sc->rx_queues[0]; in em_intr()
1805 struct tx_ring *txr = &sc->tx_queues[0].txr; in em_intr()
1806 struct rx_ring *rxr = &que->rxr; in em_intr()
1807 if_ctx_t ctx = sc->ctx; in em_intr()
1824 if (hw->mac.type >= e1000_82571 && in em_intr()
1829 * Only MSI-X interrupts have one-shot behavior by taking advantage in em_intr()
1841 sc->rx_overruns++; in em_intr()
1843 if (hw->mac.type >= e1000_82540) in em_intr()
1847 txr->tx_bytes = 0; in em_intr()
1848 txr->tx_packets = 0; in em_intr()
1849 rxr->rx_bytes = 0; in em_intr()
1850 rxr->rx_packets = 0; in em_intr()
1859 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; in em_if_rx_queue_intr_enable()
1861 E1000_WRITE_REG(&sc->hw, E1000_IMS, rxq->eims); in em_if_rx_queue_intr_enable()
1869 struct em_tx_queue *txq = &sc->tx_queues[txqid]; in em_if_tx_queue_intr_enable()
1871 E1000_WRITE_REG(&sc->hw, E1000_IMS, txq->eims); in em_if_tx_queue_intr_enable()
1879 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; in igb_if_rx_queue_intr_enable()
1881 E1000_WRITE_REG(&sc->hw, E1000_EIMS, rxq->eims); in igb_if_rx_queue_intr_enable()
1889 struct em_tx_queue *txq = &sc->tx_queues[txqid]; in igb_if_tx_queue_intr_enable()
1891 E1000_WRITE_REG(&sc->hw, E1000_EIMS, txq->eims); in igb_if_tx_queue_intr_enable()
1897 * MSI-X RX Interrupt Service routine
1904 struct e1000_softc *sc = que->sc; in em_msix_que()
1905 struct tx_ring *txr = &sc->tx_queues[que->msix].txr; in em_msix_que()
1906 struct rx_ring *rxr = &que->rxr; in em_msix_que()
1908 ++que->irqs; in em_msix_que()
1913 txr->tx_bytes = 0; in em_msix_que()
1914 txr->tx_packets = 0; in em_msix_que()
1915 rxr->rx_bytes = 0; in em_msix_que()
1916 rxr->rx_packets = 0; in em_msix_que()
1923 * MSI-X Link Fast Interrupt Service routine
1932 ++sc->link_irq; in em_msix_link()
1933 MPASS(sc->hw.back != NULL); in em_msix_link()
1934 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); in em_msix_link()
1937 sc->rx_overruns++; in em_msix_link()
1940 em_handle_link(sc->ctx); in em_msix_link()
1942 /* Re-arm unconditionally */ in em_msix_link()
1943 if (sc->hw.mac.type >= igb_mac_min) { in em_msix_link()
1944 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); in em_msix_link()
1945 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask); in em_msix_link()
1946 } else if (sc->hw.mac.type == e1000_82574) { in em_msix_link()
1947 E1000_WRITE_REG(&sc->hw, E1000_IMS, in em_msix_link()
1955 E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims); in em_msix_link()
1957 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); in em_msix_link()
1968 sc->hw.mac.get_link_status = 1; in em_handle_link()
1990 ifmr->ifm_status = IFM_AVALID; in em_if_media_status()
1991 ifmr->ifm_active = IFM_ETHER; in em_if_media_status()
1993 if (!sc->link_active) { in em_if_media_status()
1997 ifmr->ifm_status |= IFM_ACTIVE; in em_if_media_status()
1999 if ((sc->hw.phy.media_type == e1000_media_type_fiber) || in em_if_media_status()
2000 (sc->hw.phy.media_type == e1000_media_type_internal_serdes)) { in em_if_media_status()
2001 if (sc->hw.mac.type == e1000_82545) in em_if_media_status()
2003 switch (sc->link_speed) { in em_if_media_status()
2005 ifmr->ifm_active |= IFM_10_FL; in em_if_media_status()
2008 ifmr->ifm_active |= IFM_100_FX; in em_if_media_status()
2012 ifmr->ifm_active |= fiber_type | IFM_FDX; in em_if_media_status()
2016 switch (sc->link_speed) { in em_if_media_status()
2018 ifmr->ifm_active |= IFM_10_T; in em_if_media_status()
2021 ifmr->ifm_active |= IFM_100_TX; in em_if_media_status()
2024 ifmr->ifm_active |= IFM_1000_T; in em_if_media_status()
2029 if (sc->link_duplex == FULL_DUPLEX) in em_if_media_status()
2030 ifmr->ifm_active |= IFM_FDX; in em_if_media_status()
2032 ifmr->ifm_active |= IFM_HDX; in em_if_media_status()
2051 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) in em_if_media_change()
2054 switch (IFM_SUBTYPE(ifm->ifm_media)) { in em_if_media_change()
2056 sc->hw.mac.autoneg = DO_AUTO_NEG; in em_if_media_change()
2057 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; in em_if_media_change()
2062 sc->hw.mac.autoneg = DO_AUTO_NEG; in em_if_media_change()
2063 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; in em_if_media_change()
2066 sc->hw.mac.autoneg = DO_AUTO_NEG; in em_if_media_change()
2067 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { in em_if_media_change()
2068 sc->hw.phy.autoneg_advertised = ADVERTISE_100_FULL; in em_if_media_change()
2069 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; in em_if_media_change()
2071 sc->hw.phy.autoneg_advertised = ADVERTISE_100_HALF; in em_if_media_change()
2072 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; in em_if_media_change()
2076 sc->hw.mac.autoneg = DO_AUTO_NEG; in em_if_media_change()
2077 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { in em_if_media_change()
2078 sc->hw.phy.autoneg_advertised = ADVERTISE_10_FULL; in em_if_media_change()
2079 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; in em_if_media_change()
2081 sc->hw.phy.autoneg_advertised = ADVERTISE_10_HALF; in em_if_media_change()
2082 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; in em_if_media_change()
2086 sc->hw.mac.autoneg = false; in em_if_media_change()
2087 sc->hw.phy.autoneg_advertised = 0; in em_if_media_change()
2088 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) in em_if_media_change()
2089 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; in em_if_media_change()
2091 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; in em_if_media_change()
2094 sc->hw.mac.autoneg = false; in em_if_media_change()
2095 sc->hw.phy.autoneg_advertised = 0; in em_if_media_change()
2096 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) in em_if_media_change()
2097 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; in em_if_media_change()
2099 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; in em_if_media_change()
2102 device_printf(sc->dev, "Unsupported media type\n"); in em_if_media_change()
2118 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); in em_if_set_promisc()
2128 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); in em_if_set_promisc()
2136 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); in em_if_set_promisc()
2141 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); in em_if_set_promisc()
2179 mta = sc->mta; in em_if_multi_set()
2182 if (sc->hw.mac.type == e1000_82542 && in em_if_multi_set()
2183 sc->hw.revision_id == E1000_REVISION_2) { in em_if_multi_set()
2184 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); in em_if_multi_set()
2185 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) in em_if_multi_set()
2186 e1000_pci_clear_mwi(&sc->hw); in em_if_multi_set()
2188 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); in em_if_multi_set()
2195 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); in em_if_multi_set()
2197 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); in em_if_multi_set()
2208 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); in em_if_multi_set()
2210 if (sc->hw.mac.type == e1000_82542 && in em_if_multi_set()
2211 sc->hw.revision_id == E1000_REVISION_2) { in em_if_multi_set()
2212 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); in em_if_multi_set()
2214 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); in em_if_multi_set()
2216 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) in em_if_multi_set()
2217 e1000_pci_set_mwi(&sc->hw); in em_if_multi_set()
2226 * controller-specific hardware patting.
2242 struct e1000_hw *hw = &sc->hw; in em_if_update_admin_status()
2249 switch (hw->phy.media_type) { in em_if_update_admin_status()
2251 if (hw->mac.get_link_status) { in em_if_update_admin_status()
2252 if (hw->mac.type == e1000_pch_spt) in em_if_update_admin_status()
2256 link_check = !hw->mac.get_link_status; in em_if_update_admin_status()
2270 link_check = hw->mac.serdes_has_link; in em_if_update_admin_status()
2275 link_check = !hw->mac.get_link_status; in em_if_update_admin_status()
2282 if (hw->mac.type == e1000_i350) { in em_if_update_admin_status()
2288 if (link_check && (sc->link_active == 0)) { in em_if_update_admin_status()
2289 e1000_get_speed_and_duplex(hw, &sc->link_speed, in em_if_update_admin_status()
2290 &sc->link_duplex); in em_if_update_admin_status()
2291 /* Check if we must disable SPEED_MODE bit on PCI-E */ in em_if_update_admin_status()
2292 if ((sc->link_speed != SPEED_1000) && in em_if_update_admin_status()
2293 ((hw->mac.type == e1000_82571) || in em_if_update_admin_status()
2294 (hw->mac.type == e1000_82572))) { in em_if_update_admin_status()
2302 sc->link_speed, in em_if_update_admin_status()
2303 ((sc->link_duplex == FULL_DUPLEX) ? in em_if_update_admin_status()
2305 sc->link_active = 1; in em_if_update_admin_status()
2306 sc->smartspeed = 0; in em_if_update_admin_status()
2312 if (((hw->mac.type == e1000_i210) || in em_if_update_admin_status()
2313 (hw->mac.type == e1000_i211)) && in em_if_update_admin_status()
2314 (hw->phy.id == I210_I_PHY_ID)) in em_if_update_admin_status()
2317 if (hw->dev_spec._82575.media_changed && in em_if_update_admin_status()
2318 hw->mac.type >= igb_mac_min) { in em_if_update_admin_status()
2319 hw->dev_spec._82575.media_changed = false; in em_if_update_admin_status()
2320 sc->flags |= IGB_MEDIA_RESET; in em_if_update_admin_status()
2324 if (hw->mac.type < igb_mac_min) in em_if_update_admin_status()
2330 IF_Mbps(sc->link_speed)); in em_if_update_admin_status()
2331 } else if (!link_check && (sc->link_active == 1)) { in em_if_update_admin_status()
2332 sc->link_speed = 0; in em_if_update_admin_status()
2333 sc->link_duplex = 0; in em_if_update_admin_status()
2334 sc->link_active = 0; in em_if_update_admin_status()
2340 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) in em_if_update_admin_status()
2341 e1000_rar_set(hw, hw->mac.addr, 0); in em_if_update_admin_status()
2343 if (hw->mac.type < em_mac_min) in em_if_update_admin_status()
2356 sc->watchdog_events++; in em_if_watchdog_reset()
2362 * global reset on the MAC.
2373 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) in em_if_stop()
2376 e1000_reset_hw(&sc->hw); in em_if_stop()
2377 if (sc->hw.mac.type >= e1000_82544) in em_if_stop()
2378 E1000_WRITE_REG(&sc->hw, E1000_WUFC, 0); in em_if_stop()
2380 e1000_led_off(&sc->hw); in em_if_stop()
2381 e1000_cleanup_led(&sc->hw); in em_if_stop()
2396 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); in em_identify_hardware()
2399 sc->hw.vendor_id = pci_get_vendor(dev); in em_identify_hardware()
2400 sc->hw.device_id = pci_get_device(dev); in em_identify_hardware()
2401 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); in em_identify_hardware()
2402 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2); in em_identify_hardware()
2403 sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); in em_identify_hardware()
2406 if (e1000_set_mac_type(&sc->hw)) { in em_identify_hardware()
2412 if ((sc->hw.mac.type == e1000_vfadapt) || in em_identify_hardware()
2413 (sc->hw.mac.type == e1000_vfadapt_i350)) in em_identify_hardware()
2414 sc->vf_ifp = 1; in em_identify_hardware()
2416 sc->vf_ifp = 0; in em_identify_hardware()
2427 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, in em_allocate_pci_resources()
2429 if (sc->memory == NULL) { in em_allocate_pci_resources()
2434 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); in em_allocate_pci_resources()
2435 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory); in em_allocate_pci_resources()
2436 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; in em_allocate_pci_resources()
2439 if (sc->hw.mac.type < em_mac_min && sc->hw.mac.type > e1000_82543) { in em_allocate_pci_resources()
2455 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, in em_allocate_pci_resources()
2457 if (sc->ioport == NULL) { in em_allocate_pci_resources()
2462 sc->hw.io_base = 0; in em_allocate_pci_resources()
2463 sc->osdep.io_bus_space_tag = in em_allocate_pci_resources()
2464 rman_get_bustag(sc->ioport); in em_allocate_pci_resources()
2465 sc->osdep.io_bus_space_handle = in em_allocate_pci_resources()
2466 rman_get_bushandle(sc->ioport); in em_allocate_pci_resources()
2469 sc->hw.back = &sc->osdep; in em_allocate_pci_resources()
2476 * Set up the MSI-X Interrupt handlers
2483 struct em_rx_queue *rx_que = sc->rx_queues; in em_if_msix_intr_assign()
2484 struct em_tx_queue *tx_que = sc->tx_queues; in em_if_msix_intr_assign()
2489 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) { in em_if_msix_intr_assign()
2492 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, in em_if_msix_intr_assign()
2493 IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); in em_if_msix_intr_assign()
2498 sc->rx_num_queues = i + 1; in em_if_msix_intr_assign()
2502 rx_que->msix = vector; in em_if_msix_intr_assign()
2506 * in E1000_IMS -- bits 20 and 21 in em_if_msix_intr_assign()
2508 * NOTHING to do with the MSI-X vector in em_if_msix_intr_assign()
2510 if (sc->hw.mac.type == e1000_82574) { in em_if_msix_intr_assign()
2511 rx_que->eims = 1 << (20 + i); in em_if_msix_intr_assign()
2512 sc->ims |= rx_que->eims; in em_if_msix_intr_assign()
2513 sc->ivars |= (8 | rx_que->msix) << (i * 4); in em_if_msix_intr_assign()
2514 } else if (sc->hw.mac.type == e1000_82575) in em_if_msix_intr_assign()
2515 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; in em_if_msix_intr_assign()
2517 rx_que->eims = 1 << vector; in em_if_msix_intr_assign()
2522 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) { in em_if_msix_intr_assign()
2524 tx_que = &sc->tx_queues[i]; in em_if_msix_intr_assign()
2526 &sc->rx_queues[i % sc->rx_num_queues].que_irq, in em_if_msix_intr_assign()
2527 IFLIB_INTR_TX, tx_que, tx_que->me, buf); in em_if_msix_intr_assign()
2529 tx_que->msix = (vector % sc->rx_num_queues); in em_if_msix_intr_assign()
2533 * in E1000_IMS -- bits 22 and 23 in em_if_msix_intr_assign()
2535 * NOTHING to do with the MSI-X vector in em_if_msix_intr_assign()
2537 if (sc->hw.mac.type == e1000_82574) { in em_if_msix_intr_assign()
2538 tx_que->eims = 1 << (22 + i); in em_if_msix_intr_assign()
2539 sc->ims |= tx_que->eims; in em_if_msix_intr_assign()
2540 sc->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); in em_if_msix_intr_assign()
2541 } else if (sc->hw.mac.type == e1000_82575) { in em_if_msix_intr_assign()
2542 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; in em_if_msix_intr_assign()
2544 tx_que->eims = 1 << i; in em_if_msix_intr_assign()
2550 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, in em_if_msix_intr_assign()
2558 sc->linkvec = rx_vectors; in em_if_msix_intr_assign()
2559 if (sc->hw.mac.type < igb_mac_min) { in em_if_msix_intr_assign()
2560 sc->ivars |= (8 | rx_vectors) << 16; in em_if_msix_intr_assign()
2561 sc->ivars |= 0x80000000; in em_if_msix_intr_assign()
2563 sc->ims |= E1000_IMS_OTHER; in em_if_msix_intr_assign()
2568 iflib_irq_free(ctx, &sc->irq); in em_if_msix_intr_assign()
2569 rx_que = sc->rx_queues; in em_if_msix_intr_assign()
2570 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++) in em_if_msix_intr_assign()
2571 iflib_irq_free(ctx, &rx_que->que_irq); in em_if_msix_intr_assign()
2578 struct e1000_hw *hw = &sc->hw; in igb_configure_queues()
2584 if (hw->mac.type != e1000_82575) in igb_configure_queues()
2589 /* Turn on MSI-X */ in igb_configure_queues()
2590 switch (hw->mac.type) { in igb_configure_queues()
2599 for (int i = 0; i < sc->rx_num_queues; i++) { in igb_configure_queues()
2602 rx_que = &sc->rx_queues[i]; in igb_configure_queues()
2605 ivar |= (rx_que->msix | E1000_IVAR_VALID) << in igb_configure_queues()
2609 ivar |= rx_que->msix | E1000_IVAR_VALID; in igb_configure_queues()
2614 for (int i = 0; i < sc->tx_num_queues; i++) { in igb_configure_queues()
2617 tx_que = &sc->tx_queues[i]; in igb_configure_queues()
2620 ivar |= (tx_que->msix | E1000_IVAR_VALID) << in igb_configure_queues()
2624 ivar |= (tx_que->msix | E1000_IVAR_VALID) << in igb_configure_queues()
2628 sc->que_mask |= tx_que->eims; in igb_configure_queues()
2632 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; in igb_configure_queues()
2633 sc->link_mask = 1 << sc->linkvec; in igb_configure_queues()
2638 for (int i = 0; i < sc->rx_num_queues; i++) { in igb_configure_queues()
2641 rx_que = &sc->rx_queues[i]; in igb_configure_queues()
2644 ivar |= rx_que->msix | E1000_IVAR_VALID; in igb_configure_queues()
2647 ivar |= (rx_que->msix | E1000_IVAR_VALID) << in igb_configure_queues()
2651 sc->que_mask |= rx_que->eims; in igb_configure_queues()
2654 for (int i = 0; i < sc->tx_num_queues; i++) { in igb_configure_queues()
2657 tx_que = &sc->tx_queues[i]; in igb_configure_queues()
2660 ivar |= (tx_que->msix | E1000_IVAR_VALID) << in igb_configure_queues()
2664 ivar |= (tx_que->msix | E1000_IVAR_VALID) << in igb_configure_queues()
2668 sc->que_mask |= tx_que->eims; in igb_configure_queues()
2672 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; in igb_configure_queues()
2673 sc->link_mask = 1 << sc->linkvec; in igb_configure_queues()
2678 /* enable MSI-X support*/ in igb_configure_queues()
2681 /* Auto-Mask interrupts upon ICR read. */ in igb_configure_queues()
2687 for (int i = 0; i < sc->rx_num_queues; i++) { in igb_configure_queues()
2688 rx_que = &sc->rx_queues[i]; in igb_configure_queues()
2691 rx_que->eims = tmp; in igb_configure_queues()
2693 rx_que->eims); in igb_configure_queues()
2694 sc->que_mask |= rx_que->eims; in igb_configure_queues()
2698 E1000_WRITE_REG(hw, E1000_MSIXBM(sc->linkvec), in igb_configure_queues()
2700 sc->link_mask |= E1000_EIMS_OTHER; in igb_configure_queues()
2709 if (hw->mac.type == e1000_82575) in igb_configure_queues()
2714 for (int i = 0; i < sc->rx_num_queues; i++) { in igb_configure_queues()
2715 rx_que = &sc->rx_queues[i]; in igb_configure_queues()
2716 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); in igb_configure_queues()
2727 struct em_rx_queue *que = sc->rx_queues; in em_free_pci_resources()
2730 /* Release all MSI-X queue resources */ in em_free_pci_resources()
2731 if (sc->intr_type == IFLIB_INTR_MSIX) in em_free_pci_resources()
2732 iflib_irq_free(ctx, &sc->irq); in em_free_pci_resources()
2735 for (int i = 0; i < sc->rx_num_queues; i++, que++) { in em_free_pci_resources()
2736 iflib_irq_free(ctx, &que->que_irq); in em_free_pci_resources()
2740 if (sc->memory != NULL) { in em_free_pci_resources()
2742 rman_get_rid(sc->memory), sc->memory); in em_free_pci_resources()
2743 sc->memory = NULL; in em_free_pci_resources()
2746 if (sc->flash != NULL) { in em_free_pci_resources()
2748 rman_get_rid(sc->flash), sc->flash); in em_free_pci_resources()
2749 sc->flash = NULL; in em_free_pci_resources()
2752 if (sc->ioport != NULL) { in em_free_pci_resources()
2754 rman_get_rid(sc->ioport), sc->ioport); in em_free_pci_resources()
2755 sc->ioport = NULL; in em_free_pci_resources()
2759 /* Set up MSI or MSI-X */
2765 if (sc->hw.mac.type == e1000_82574) { in em_setup_msix()
2781 if (sc->link_active || (sc->hw.phy.type != e1000_phy_igp) || in lem_smartspeed()
2782 sc->hw.mac.autoneg == 0 || in lem_smartspeed()
2783 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) in lem_smartspeed()
2786 if (sc->smartspeed == 0) { in lem_smartspeed()
2788 * we assume back-to-back */ in lem_smartspeed()
2789 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); in lem_smartspeed()
2792 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); in lem_smartspeed()
2794 e1000_read_phy_reg(&sc->hw, in lem_smartspeed()
2798 e1000_write_phy_reg(&sc->hw, in lem_smartspeed()
2800 sc->smartspeed++; in lem_smartspeed()
2801 if(sc->hw.mac.autoneg && in lem_smartspeed()
2802 !e1000_copper_link_autoneg(&sc->hw) && in lem_smartspeed()
2803 !e1000_read_phy_reg(&sc->hw, in lem_smartspeed()
2807 e1000_write_phy_reg(&sc->hw, in lem_smartspeed()
2813 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { in lem_smartspeed()
2815 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); in lem_smartspeed()
2817 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); in lem_smartspeed()
2818 if(sc->hw.mac.autoneg && in lem_smartspeed()
2819 !e1000_copper_link_autoneg(&sc->hw) && in lem_smartspeed()
2820 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { in lem_smartspeed()
2823 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); in lem_smartspeed()
2827 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) in lem_smartspeed()
2828 sc->smartspeed = 0; in lem_smartspeed()
2839 device_t dev = sc->dev; in igb_init_dmac()
2840 struct e1000_hw *hw = &sc->hw; in igb_init_dmac()
2845 if (hw->mac.type == e1000_i211) in igb_init_dmac()
2848 max_frame_size = sc->shared->isc_max_frame_size; in igb_init_dmac()
2849 if (hw->mac.type > e1000_82580) { in igb_init_dmac()
2851 if (sc->dmac == 0) { /* Disabling it */ in igb_init_dmac()
2860 hwm = 64 * pba - max_frame_size / 16; in igb_init_dmac()
2861 if (hwm < 64 * (pba - 6)) in igb_init_dmac()
2862 hwm = 64 * (pba - 6); in igb_init_dmac()
2870 dmac = pba - max_frame_size / 512; in igb_init_dmac()
2871 if (dmac < pba - 10) in igb_init_dmac()
2872 dmac = pba - 10; in igb_init_dmac()
2887 if (hw->mac.type == e1000_i354) { in igb_init_dmac()
2891 reg |= ((sc->dmac * 5) >> 6); in igb_init_dmac()
2893 reg |= (sc->dmac >> 5); in igb_init_dmac()
2895 reg |= (sc->dmac >> 5); in igb_init_dmac()
2904 if (hw->mac.type == e1000_i350) in igb_init_dmac()
2910 if (hw->mac.type == e1000_i354) { in igb_init_dmac()
2924 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - in igb_init_dmac()
2932 } else if (hw->mac.type == e1000_82580) { in igb_init_dmac()
2943 * em_flush_tx_ring - remove all descriptors from the tx_ring
2953 struct e1000_hw *hw = &sc->hw; in em_flush_tx_ring()
2954 struct tx_ring *txr = &sc->tx_queues->txr; in em_flush_tx_ring()
2962 txd = &txr->tx_base[txr->tx_cidx_processed]; in em_flush_tx_ring()
2965 txd->buffer_addr = txr->tx_paddr; in em_flush_tx_ring()
2966 txd->lower.data = htole32(txd_lower | size); in em_flush_tx_ring()
2967 txd->upper.data = 0; in em_flush_tx_ring()
2972 E1000_WRITE_REG(hw, E1000_TDT(0), txr->tx_cidx_processed); in em_flush_tx_ring()
2978 * em_flush_rx_ring - remove all descriptors from the rx_ring
2985 struct e1000_hw *hw = &sc->hw; in em_flush_rx_ring()
3012 * em_flush_desc_rings - remove all descriptors from the descriptor rings
3024 struct e1000_hw *hw = &sc->hw; in em_flush_desc_rings()
3025 device_t dev = sc->dev; in em_flush_desc_rings()
3060 struct e1000_hw *hw = &sc->hw; in em_reset()
3069 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || in em_reset()
3070 hw->mac.type == e1000_82572)) { in em_reset()
3084 switch (hw->mac.type) { in em_reset()
3088 if (hw->mac.max_frame_size > 8192) in em_reset()
3113 if (hw->mac.max_frame_size > 4096) in em_reset()
3150 if (hw->mac.max_frame_size > 8192) in em_reset()
3157 if ((hw->mac.type == e1000_82575) && (if_getmtu(ifp) > ETHERMTU)) { in em_reset()
3162 min_tx = (hw->mac.max_frame_size + in em_reset()
3163 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; in em_reset()
3166 min_rx = hw->mac.max_frame_size; in em_reset()
3170 ((min_tx - tx_space) < pba)) { in em_reset()
3171 pba = pba - (min_tx - tx_space); in em_reset()
3182 if (hw->mac.type < igb_mac_min) in em_reset()
3190 * - High water mark should allow for at least two frames to be in em_reset()
3192 * - Low water mark works best when it is very near the high water in em_reset()
3200 * - The pause time is fairly large at 1000 x 512ns = 512 usec. in em_reset()
3203 hw->fc.high_water = rx_buffer_size - in em_reset()
3204 roundup2(hw->mac.max_frame_size, 1024); in em_reset()
3205 hw->fc.low_water = hw->fc.high_water - 1500; in em_reset()
3207 if (sc->fc) /* locally set flow control value? */ in em_reset()
3208 hw->fc.requested_mode = sc->fc; in em_reset()
3210 hw->fc.requested_mode = e1000_fc_full; in em_reset()
3212 if (hw->mac.type == e1000_80003es2lan) in em_reset()
3213 hw->fc.pause_time = 0xFFFF; in em_reset()
3215 hw->fc.pause_time = EM_FC_PAUSE_TIME; in em_reset()
3217 hw->fc.send_xon = true; in em_reset()
3220 switch (hw->mac.type) { in em_reset()
3223 hw->fc.requested_mode = e1000_fc_rx_pause; in em_reset()
3224 hw->fc.pause_time = 0xFFFF; /* override */ in em_reset()
3226 hw->fc.high_water = 0x3500; in em_reset()
3227 hw->fc.low_water = 0x1500; in em_reset()
3229 hw->fc.high_water = 0x5000; in em_reset()
3230 hw->fc.low_water = 0x3000; in em_reset()
3232 hw->fc.refresh_time = 0x1000; in em_reset()
3242 hw->fc.high_water = 0x5C20; in em_reset()
3243 hw->fc.low_water = 0x5048; in em_reset()
3244 hw->fc.pause_time = 0x0650; in em_reset()
3245 hw->fc.refresh_time = 0x0400; in em_reset()
3254 /* 8-byte granularity */ in em_reset()
3255 hw->fc.low_water = hw->fc.high_water - 8; in em_reset()
3264 /* 16-byte granularity */ in em_reset()
3265 hw->fc.low_water = hw->fc.high_water - 16; in em_reset()
3270 hw->fc.high_water = 0x2800; in em_reset()
3271 hw->fc.low_water = hw->fc.high_water - 8; in em_reset()
3276 if (hw->mac.type == e1000_80003es2lan) in em_reset()
3277 hw->fc.pause_time = 0xFFFF; in em_reset()
3282 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) in em_reset()
3287 if (hw->mac.type >= igb_mac_min) { in em_reset()
3293 if (sc->flags & IGB_MEDIA_RESET) { in em_reset()
3296 sc->flags &= ~IGB_MEDIA_RESET; in em_reset()
3298 /* and a re-init */ in em_reset()
3303 if (hw->mac.type >= igb_mac_min) in em_reset()
3307 sc->pba = pba; in em_reset()
3325 struct e1000_hw *hw = &sc->hw; in em_initialize_rss_mapping()
3346 q = (i % sc->rx_num_queues) << 7; in em_initialize_rss_mapping()
3364 struct e1000_hw *hw = &sc->hw; in igb_initialize_rss_mapping()
3371 if (hw->mac.type == e1000_82575) in igb_initialize_rss_mapping()
3380 * This just allocates buckets to queues using round-robin in igb_initialize_rss_mapping()
3405 queue_id = queue_id % sc->rx_num_queues; in igb_initialize_rss_mapping()
3407 queue_id = (i % sc->rx_num_queues); in igb_initialize_rss_mapping()
3466 if_softc_ctx_t scctx = sc->shared; in em_setup_interface()
3471 if (sc->tx_num_queues == 1) { in em_setup_interface()
3472 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); in em_setup_interface()
3480 if (sc->hw.phy.media_type == e1000_media_type_fiber || in em_setup_interface()
3481 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { in em_setup_interface()
3484 if (sc->hw.mac.type == e1000_82545) in em_setup_interface()
3486 ifmedia_add(sc->media, in em_setup_interface()
3488 ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL); in em_setup_interface()
3490 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); in em_setup_interface()
3491 ifmedia_add(sc->media, in em_setup_interface()
3493 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); in em_setup_interface()
3494 ifmedia_add(sc->media, in em_setup_interface()
3496 if (sc->hw.phy.type != e1000_phy_ife) { in em_setup_interface()
3497 ifmedia_add(sc->media, in em_setup_interface()
3499 ifmedia_add(sc->media, in em_setup_interface()
3503 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); in em_setup_interface()
3504 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); in em_setup_interface()
3513 if_softc_ctx_t scctx = sc->shared; in em_if_tx_queues_alloc()
3518 MPASS(sc->tx_num_queues > 0); in em_if_tx_queues_alloc()
3519 MPASS(sc->tx_num_queues == ntxqsets); in em_if_tx_queues_alloc()
3522 if (!(sc->tx_queues = in em_if_tx_queues_alloc()
3524 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { in em_if_tx_queues_alloc()
3530 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) { in em_if_tx_queues_alloc()
3533 struct tx_ring *txr = &que->txr; in em_if_tx_queues_alloc()
3534 txr->sc = que->sc = sc; in em_if_tx_queues_alloc()
3535 que->me = txr->me = i; in em_if_tx_queues_alloc()
3538 if (!(txr->tx_rsq = in em_if_tx_queues_alloc()
3539 (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], in em_if_tx_queues_alloc()
3546 for (j = 0; j < scctx->isc_ntxd[0]; j++) in em_if_tx_queues_alloc()
3547 txr->tx_rsq[j] = QIDX_INVALID; in em_if_tx_queues_alloc()
3549 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; in em_if_tx_queues_alloc()
3550 txr->tx_paddr = paddrs[i*ntxqs]; in em_if_tx_queues_alloc()
3555 "allocated for %d tx_queues\n", sc->tx_num_queues); in em_if_tx_queues_alloc()
3571 MPASS(sc->rx_num_queues > 0); in em_if_rx_queues_alloc()
3572 MPASS(sc->rx_num_queues == nrxqsets); in em_if_rx_queues_alloc()
3575 if (!(sc->rx_queues = in em_if_rx_queues_alloc()
3577 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { in em_if_rx_queues_alloc()
3584 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { in em_if_rx_queues_alloc()
3586 struct rx_ring *rxr = &que->rxr; in em_if_rx_queues_alloc()
3587 rxr->sc = que->sc = sc; in em_if_rx_queues_alloc()
3588 rxr->que = que; in em_if_rx_queues_alloc()
3589 que->me = rxr->me = i; in em_if_rx_queues_alloc()
3592 rxr->rx_base = in em_if_rx_queues_alloc()
3594 rxr->rx_paddr = paddrs[i*nrxqs]; in em_if_rx_queues_alloc()
3599 "allocated for %d rx_queues\n", sc->rx_num_queues); in em_if_rx_queues_alloc()
3611 struct em_tx_queue *tx_que = sc->tx_queues; in em_if_queues_free()
3612 struct em_rx_queue *rx_que = sc->rx_queues; in em_if_queues_free()
3615 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { in em_if_queues_free()
3616 struct tx_ring *txr = &tx_que->txr; in em_if_queues_free()
3617 if (txr->tx_rsq == NULL) in em_if_queues_free()
3620 free(txr->tx_rsq, M_DEVBUF); in em_if_queues_free()
3621 txr->tx_rsq = NULL; in em_if_queues_free()
3623 free(sc->tx_queues, M_DEVBUF); in em_if_queues_free()
3624 sc->tx_queues = NULL; in em_if_queues_free()
3628 free(sc->rx_queues, M_DEVBUF); in em_if_queues_free()
3629 sc->rx_queues = NULL; in em_if_queues_free()
3642 if_softc_ctx_t scctx = sc->shared; in em_initialize_transmit_unit()
3645 struct e1000_hw *hw = &sc->hw; in em_initialize_transmit_unit()
3650 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { in em_initialize_transmit_unit()
3654 que = &sc->tx_queues[i]; in em_initialize_transmit_unit()
3655 txr = &que->txr; in em_initialize_transmit_unit()
3656 bus_addr = txr->tx_paddr; in em_initialize_transmit_unit()
3659 offp = (caddr_t)&txr->csum_flags; in em_initialize_transmit_unit()
3661 bzero(offp, endp - offp); in em_initialize_transmit_unit()
3665 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); in em_initialize_transmit_unit()
3688 switch (hw->mac.type) { in em_initialize_transmit_unit()
3700 if (hw->phy.media_type == e1000_media_type_fiber || in em_initialize_transmit_unit()
3701 hw->phy.media_type == e1000_media_type_internal_serdes) in em_initialize_transmit_unit()
3709 if (hw->mac.type < igb_mac_min) { in em_initialize_transmit_unit()
3711 E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value); in em_initialize_transmit_unit()
3713 if (sc->tx_int_delay.value > 0) in em_initialize_transmit_unit()
3714 sc->txd_cmd |= E1000_TXD_CMD_IDE; in em_initialize_transmit_unit()
3717 if (hw->mac.type >= e1000_82540) in em_initialize_transmit_unit()
3718 E1000_WRITE_REG(hw, E1000_TADV, sc->tx_abs_int_delay.value); in em_initialize_transmit_unit()
3720 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { in em_initialize_transmit_unit()
3724 } else if (hw->mac.type == e1000_80003es2lan) { in em_initialize_transmit_unit()
3732 } else if (hw->mac.type == e1000_82574) { in em_initialize_transmit_unit()
3735 if ( sc->tx_num_queues > 1) { in em_initialize_transmit_unit()
3749 if (hw->mac.type >= e1000_82571 && hw->mac.type < igb_mac_min) in em_initialize_transmit_unit()
3756 if (hw->mac.type == e1000_pch_spt) { in em_initialize_transmit_unit()
3761 /* i218-i219 Specification Update 1.5.4.5 */ in em_initialize_transmit_unit()
3774 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1)
3780 if_softc_ctx_t scctx = sc->shared; in em_initialize_receive_unit()
3782 struct e1000_hw *hw = &sc->hw; in em_initialize_receive_unit()
3795 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) in em_initialize_receive_unit()
3802 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); in em_initialize_receive_unit()
3818 if (hw->mac.type < igb_mac_min) { in em_initialize_receive_unit()
3819 if (hw->mac.type >= e1000_82540) { in em_initialize_receive_unit()
3821 sc->rx_abs_int_delay.value); in em_initialize_receive_unit()
3834 if (hw->mac.type == e1000_82573) in em_initialize_receive_unit()
3838 sc->rx_int_delay.value); in em_initialize_receive_unit()
3841 if (hw->mac.type >= em_mac_min) { in em_initialize_receive_unit()
3848 * When using MSI-X interrupts we need to throttle in em_initialize_receive_unit()
3851 if (hw->mac.type == e1000_82574) { in em_initialize_receive_unit()
3865 if (hw->mac.type > e1000_82575) in em_initialize_receive_unit()
3867 else if (hw->mac.type < em_mac_min && in em_initialize_receive_unit()
3872 if (hw->mac.type > e1000_82575) in em_initialize_receive_unit()
3874 else if (hw->mac.type < em_mac_min) in em_initialize_receive_unit()
3878 if (sc->rx_num_queues > 1) { in em_initialize_receive_unit()
3882 if (hw->mac.type >= igb_mac_min) in em_initialize_receive_unit()
3889 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { in em_initialize_receive_unit()
3890 struct rx_ring *rxr = &que->rxr; in em_initialize_receive_unit()
3892 u64 bus_addr = rxr->rx_paddr; in em_initialize_receive_unit()
3894 u32 rdt = sc->rx_num_queues -1; /* default */ in em_initialize_receive_unit()
3898 scctx->isc_nrxd[0] * in em_initialize_receive_unit()
3914 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan || in em_initialize_receive_unit()
3915 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) { in em_initialize_receive_unit()
3918 } else if (hw->mac.type == e1000_82574) { in em_initialize_receive_unit()
3919 for (int i = 0; i < sc->rx_num_queues; i++) { in em_initialize_receive_unit()
3927 } else if (hw->mac.type >= igb_mac_min) { in em_initialize_receive_unit()
3931 psize = scctx->isc_max_frame_size; in em_initialize_receive_unit()
3936 if (sc->vf_ifp) in em_initialize_receive_unit()
3943 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> in em_initialize_receive_unit()
3950 * This drops frames rather than hanging the RX MAC for all in em_initialize_receive_unit()
3953 if ((sc->rx_num_queues > 1) && in em_initialize_receive_unit()
3954 (sc->fc == e1000_fc_none || in em_initialize_receive_unit()
3955 sc->fc == e1000_fc_rx_pause)) { in em_initialize_receive_unit()
3959 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; in em_initialize_receive_unit()
3961 struct rx_ring *rxr = &que->rxr; in em_initialize_receive_unit()
3962 u64 bus_addr = rxr->rx_paddr; in em_initialize_receive_unit()
3966 /* Configure for header split? -- ignore for now */ in em_initialize_receive_unit()
3967 rxr->hdr_split = igb_header_split; in em_initialize_receive_unit()
3973 scctx->isc_nrxd[0] * in em_initialize_receive_unit()
3989 } else if (hw->mac.type >= e1000_pch2lan) { in em_initialize_receive_unit()
4000 if (hw->mac.type < igb_mac_min) { in em_initialize_receive_unit()
4001 if (sc->rx_mbuf_sz > 2048 && sc->rx_mbuf_sz <= 4096) in em_initialize_receive_unit()
4003 else if (sc->rx_mbuf_sz > 4096 && sc->rx_mbuf_sz <= 8192) in em_initialize_receive_unit()
4005 else if (sc->rx_mbuf_sz > 8192) in em_initialize_receive_unit()
4037 sc->shadow_vfta[index] |= (1 << bit); in em_if_vlan_register()
4038 ++sc->num_vlans; in em_if_vlan_register()
4050 sc->shadow_vfta[index] &= ~(1 << bit); in em_if_vlan_unregister()
4051 --sc->num_vlans; in em_if_vlan_unregister()
4076 if (sc->shadow_vfta[i] != 0) in em_if_vlan_filter_used()
4085 struct e1000_hw *hw = &sc->hw; in em_if_vlan_filter_enable()
4097 struct e1000_hw *hw = &sc->hw; in em_if_vlan_filter_disable()
4108 struct e1000_hw *hw = &sc->hw; in em_if_vlan_filter_write()
4110 if (sc->vf_ifp) in em_if_vlan_filter_write()
4114 if (hw->mac.type < em_mac_min) in em_if_vlan_filter_write()
4115 em_if_intr_disable(sc->ctx); in em_if_vlan_filter_write()
4118 if (sc->shadow_vfta[i] != 0) { in em_if_vlan_filter_write()
4120 if (sc->vf_ifp) in em_if_vlan_filter_write()
4121 e1000_vfta_set_vf(hw, sc->shadow_vfta[i], in em_if_vlan_filter_write()
4124 e1000_write_vfta(hw, i, sc->shadow_vfta[i]); in em_if_vlan_filter_write()
4127 /* Re-enable interrupts for lem-class devices */ in em_if_vlan_filter_write()
4128 if (hw->mac.type < em_mac_min) in em_if_vlan_filter_write()
4129 em_if_intr_enable(sc->ctx); in em_if_vlan_filter_write()
4136 struct e1000_hw *hw = &sc->hw; in em_setup_vlan_hw_support()
4143 if (sc->vf_ifp) in em_setup_vlan_hw_support()
4179 struct e1000_hw *hw = &sc->hw; in em_if_intr_enable()
4182 if (sc->intr_type == IFLIB_INTR_MSIX) { in em_if_intr_enable()
4183 E1000_WRITE_REG(hw, EM_EIAC, sc->ims); in em_if_intr_enable()
4184 ims_mask |= sc->ims; in em_if_intr_enable()
4195 struct e1000_hw *hw = &sc->hw; in em_if_intr_disable()
4197 if (sc->intr_type == IFLIB_INTR_MSIX) in em_if_intr_disable()
4207 struct e1000_hw *hw = &sc->hw; in igb_if_intr_enable()
4210 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { in igb_if_intr_enable()
4211 mask = (sc->que_mask | sc->link_mask); in igb_if_intr_enable()
4225 struct e1000_hw *hw = &sc->hw; in igb_if_intr_disable()
4227 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { in igb_if_intr_disable()
4245 if (sc->has_manage) { in em_init_manageability()
4246 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); in em_init_manageability()
4247 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); in em_init_manageability()
4258 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); in em_init_manageability()
4259 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); in em_init_manageability()
4270 if (sc->has_manage) { in em_release_manageability()
4271 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); in em_release_manageability()
4273 /* re-enable hardware interception of ARP */ in em_release_manageability()
4277 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); in em_release_manageability()
4292 if (sc->vf_ifp) in em_get_hw_control()
4295 if (sc->hw.mac.type == e1000_82573) { in em_get_hw_control()
4296 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); in em_get_hw_control()
4297 E1000_WRITE_REG(&sc->hw, E1000_SWSM, in em_get_hw_control()
4302 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); in em_get_hw_control()
4303 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, in em_get_hw_control()
4318 if (!sc->has_manage) in em_release_hw_control()
4321 if (sc->hw.mac.type == e1000_82573) { in em_release_hw_control()
4322 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); in em_release_hw_control()
4323 E1000_WRITE_REG(&sc->hw, E1000_SWSM, in em_release_hw_control()
4328 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); in em_release_hw_control()
4329 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, in em_release_hw_control()
4353 if (!em_unsupported_tso && sc->link_speed && in em_automask_tso()
4354 sc->link_speed != SPEED_1000 && in em_automask_tso()
4355 scctx->isc_capenable & IFCAP_TSO) { in em_automask_tso()
4356 device_printf(sc->dev, in em_automask_tso()
4358 sc->tso_automasked = scctx->isc_capenable & IFCAP_TSO; in em_automask_tso()
4359 scctx->isc_capenable &= ~IFCAP_TSO; in em_automask_tso()
4364 } else if (sc->link_speed == SPEED_1000 && sc->tso_automasked) { in em_automask_tso()
4365 device_printf(sc->dev, "Re-enabling TSO for GbE.\n"); in em_automask_tso()
4366 scctx->isc_capenable |= sc->tso_automasked; in em_automask_tso()
4367 if_setcapenablebit(ifp, sc->tso_automasked, 0); in em_automask_tso()
4368 sc->tso_automasked = 0; in em_automask_tso()
4379 ** to both system management and wake-on-lan for
4389 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw); in em_get_wakeup()
4392 switch (sc->hw.mac.type) { in em_get_wakeup()
4397 e1000_read_nvm(&sc->hw, in em_get_wakeup()
4403 if (sc->hw.bus.func == 1) { in em_get_wakeup()
4404 e1000_read_nvm(&sc->hw, in em_get_wakeup()
4408 e1000_read_nvm(&sc->hw, in em_get_wakeup()
4413 sc->has_amt = true; in em_get_wakeup()
4418 if (sc->hw.bus.func == 1) { in em_get_wakeup()
4419 e1000_read_nvm(&sc->hw, in em_get_wakeup()
4423 e1000_read_nvm(&sc->hw, in em_get_wakeup()
4443 sc->has_amt = true; in em_get_wakeup()
4444 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC); in em_get_wakeup()
4447 e1000_read_nvm(&sc->hw, in em_get_wakeup()
4452 sc->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); in em_get_wakeup()
4461 sc->wol = 0; in em_get_wakeup()
4467 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & in em_get_wakeup()
4469 sc->wol = 0; in em_get_wakeup()
4472 /* if quad port adapter, disable WoL on all but port A */ in em_get_wakeup()
4474 sc->wol = 0; in em_get_wakeup()
4482 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & in em_get_wakeup()
4484 sc->wol = 0; in em_get_wakeup()
4489 /* if quad port adapter, disable WoL on all but port A */ in em_get_wakeup()
4491 sc->wol = 0; in em_get_wakeup()
4517 * Determine type of Wakeup: note that wol in em_enable_wakeup()
4521 sc->wol &= ~E1000_WUFC_MAG; in em_enable_wakeup()
4524 sc->wol &= ~E1000_WUFC_EX; in em_enable_wakeup()
4527 sc->wol &= ~E1000_WUFC_MC; in em_enable_wakeup()
4529 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); in em_enable_wakeup()
4531 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); in em_enable_wakeup()
4534 if (!(sc->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) in em_enable_wakeup()
4538 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); in em_enable_wakeup()
4540 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); in em_enable_wakeup()
4543 if (sc->hw.phy.media_type == e1000_media_type_fiber || in em_enable_wakeup()
4544 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { in em_enable_wakeup()
4545 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); in em_enable_wakeup()
4547 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, ctrl_ext); in em_enable_wakeup()
4550 if ((sc->hw.mac.type == e1000_ich8lan) || in em_enable_wakeup()
4551 (sc->hw.mac.type == e1000_pchlan) || in em_enable_wakeup()
4552 (sc->hw.mac.type == e1000_ich9lan) || in em_enable_wakeup()
4553 (sc->hw.mac.type == e1000_ich10lan)) in em_enable_wakeup()
4554 e1000_suspend_workarounds_ich8lan(&sc->hw); in em_enable_wakeup()
4556 if ( sc->hw.mac.type >= e1000_pchlan) { in em_enable_wakeup()
4561 /* Enable wakeup by the MAC */ in em_enable_wakeup()
4562 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); in em_enable_wakeup()
4563 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); in em_enable_wakeup()
4566 if (sc->hw.phy.type == e1000_phy_igp_3) in em_enable_wakeup()
4567 e1000_igp3_phy_powerdown_workaround_ich8lan(&sc->hw); in em_enable_wakeup()
4577 * WOL in the newer chipset interfaces (pchlan)
4583 struct e1000_hw *hw = &sc->hw; in em_enable_phy_wakeup()
4587 /* copy MAC RARs to PHY RARs */ in em_enable_phy_wakeup()
4590 /* copy MAC MTA to PHY MTA */ in em_enable_phy_wakeup()
4591 for (int i = 0; i < hw->mac.mta_reg_count; i++) { in em_enable_phy_wakeup()
4618 /* enable PHY wakeup in MAC register */ in em_enable_phy_wakeup()
4621 E1000_WRITE_REG(hw, E1000_WUFC, sc->wol); in em_enable_phy_wakeup()
4624 e1000_write_phy_reg(hw, BM_WUFC, sc->wol); in em_enable_phy_wakeup()
4628 ret = hw->phy.ops.acquire(hw); in em_enable_phy_wakeup()
4645 hw->phy.ops.release(hw); in em_enable_phy_wakeup()
4656 e1000_setup_led(&sc->hw); in em_if_led_func()
4657 e1000_led_on(&sc->hw); in em_if_led_func()
4659 e1000_led_off(&sc->hw); in em_if_led_func()
4660 e1000_cleanup_led(&sc->hw); in em_if_led_func()
4672 device_t dev = sc->dev; in em_disable_aspm()
4674 switch (sc->hw.mac.type) { in em_disable_aspm()
4703 u64 prev_xoffrxc = sc->stats.xoffrxc; in em_update_stats_counters()
4705 if(sc->hw.phy.media_type == e1000_media_type_copper || in em_update_stats_counters()
4706 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { in em_update_stats_counters()
4707 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); in em_update_stats_counters()
4708 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC); in em_update_stats_counters()
4710 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); in em_update_stats_counters()
4711 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC); in em_update_stats_counters()
4712 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC); in em_update_stats_counters()
4713 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); in em_update_stats_counters()
4715 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC); in em_update_stats_counters()
4716 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); in em_update_stats_counters()
4717 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC); in em_update_stats_counters()
4718 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC); in em_update_stats_counters()
4719 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); in em_update_stats_counters()
4720 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); in em_update_stats_counters()
4721 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); in em_update_stats_counters()
4722 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); in em_update_stats_counters()
4727 if (sc->stats.xoffrxc != prev_xoffrxc) in em_update_stats_counters()
4728 sc->shared->isc_pause_frames = 1; in em_update_stats_counters()
4729 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); in em_update_stats_counters()
4730 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); in em_update_stats_counters()
4731 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); in em_update_stats_counters()
4732 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); in em_update_stats_counters()
4733 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); in em_update_stats_counters()
4734 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); in em_update_stats_counters()
4735 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); in em_update_stats_counters()
4736 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); in em_update_stats_counters()
4737 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); in em_update_stats_counters()
4738 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); in em_update_stats_counters()
4739 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); in em_update_stats_counters()
4740 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); in em_update_stats_counters()
4742 /* For the 64-bit byte counters the low dword must be read first. */ in em_update_stats_counters()
4745 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCL) + in em_update_stats_counters()
4746 ((u64)E1000_READ_REG(&sc->hw, E1000_GORCH) << 32); in em_update_stats_counters()
4747 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCL) + in em_update_stats_counters()
4748 ((u64)E1000_READ_REG(&sc->hw, E1000_GOTCH) << 32); in em_update_stats_counters()
4750 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); in em_update_stats_counters()
4751 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC); in em_update_stats_counters()
4752 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC); in em_update_stats_counters()
4753 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC); in em_update_stats_counters()
4754 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC); in em_update_stats_counters()
4756 sc->stats.mgprc += E1000_READ_REG(&sc->hw, E1000_MGTPRC); in em_update_stats_counters()
4757 sc->stats.mgpdc += E1000_READ_REG(&sc->hw, E1000_MGTPDC); in em_update_stats_counters()
4758 sc->stats.mgptc += E1000_READ_REG(&sc->hw, E1000_MGTPTC); in em_update_stats_counters()
4760 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH); in em_update_stats_counters()
4761 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH); in em_update_stats_counters()
4763 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR); in em_update_stats_counters()
4764 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT); in em_update_stats_counters()
4765 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); in em_update_stats_counters()
4766 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); in em_update_stats_counters()
4767 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); in em_update_stats_counters()
4768 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); in em_update_stats_counters()
4769 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); in em_update_stats_counters()
4770 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); in em_update_stats_counters()
4771 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); in em_update_stats_counters()
4772 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); in em_update_stats_counters()
4776 sc->stats.iac += E1000_READ_REG(&sc->hw, E1000_IAC); in em_update_stats_counters()
4777 sc->stats.icrxptc += E1000_READ_REG(&sc->hw, E1000_ICRXPTC); in em_update_stats_counters()
4778 sc->stats.icrxatc += E1000_READ_REG(&sc->hw, E1000_ICRXATC); in em_update_stats_counters()
4779 sc->stats.ictxptc += E1000_READ_REG(&sc->hw, E1000_ICTXPTC); in em_update_stats_counters()
4780 sc->stats.ictxatc += E1000_READ_REG(&sc->hw, E1000_ICTXATC); in em_update_stats_counters()
4781 sc->stats.ictxqec += E1000_READ_REG(&sc->hw, E1000_ICTXQEC); in em_update_stats_counters()
4782 sc->stats.ictxqmtc += E1000_READ_REG(&sc->hw, E1000_ICTXQMTC); in em_update_stats_counters()
4783 sc->stats.icrxdmtc += E1000_READ_REG(&sc->hw, E1000_ICRXDMTC); in em_update_stats_counters()
4784 sc->stats.icrxoc += E1000_READ_REG(&sc->hw, E1000_ICRXOC); in em_update_stats_counters()
4786 if (sc->hw.mac.type >= e1000_82543) { in em_update_stats_counters()
4787 sc->stats.algnerrc += in em_update_stats_counters()
4788 E1000_READ_REG(&sc->hw, E1000_ALGNERRC); in em_update_stats_counters()
4789 sc->stats.rxerrc += in em_update_stats_counters()
4790 E1000_READ_REG(&sc->hw, E1000_RXERRC); in em_update_stats_counters()
4791 sc->stats.tncrs += in em_update_stats_counters()
4792 E1000_READ_REG(&sc->hw, E1000_TNCRS); in em_update_stats_counters()
4793 sc->stats.cexterr += in em_update_stats_counters()
4794 E1000_READ_REG(&sc->hw, E1000_CEXTERR); in em_update_stats_counters()
4795 sc->stats.tsctc += in em_update_stats_counters()
4796 E1000_READ_REG(&sc->hw, E1000_TSCTC); in em_update_stats_counters()
4797 sc->stats.tsctfc += in em_update_stats_counters()
4798 E1000_READ_REG(&sc->hw, E1000_TSCTFC); in em_update_stats_counters()
4810 return (sc->stats.colc); in em_if_get_counter()
4812 return (sc->dropped_pkts + sc->stats.rxerrc + in em_if_get_counter()
4813 sc->stats.crcerrs + sc->stats.algnerrc + in em_if_get_counter()
4814 sc->stats.ruc + sc->stats.roc + in em_if_get_counter()
4815 sc->stats.mpc + sc->stats.cexterr); in em_if_get_counter()
4817 return (sc->stats.ecol + sc->stats.latecol + in em_if_get_counter()
4818 sc->watchdog_events); in em_if_get_counter()
4824 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized
4842 /* Export a single 32-bit register via a read-only sysctl. */
4849 sc = oidp->oid_arg1; in em_sysctl_reg_handler()
4850 val = E1000_READ_REG(&sc->hw, oidp->oid_arg2); in em_sysctl_reg_handler()
4864 bool tx = oidp->oid_arg2; in em_sysctl_interrupt_rate_handler()
4867 tque = oidp->oid_arg1; in em_sysctl_interrupt_rate_handler()
4868 hw = &tque->sc->hw; in em_sysctl_interrupt_rate_handler()
4869 if (hw->mac.type >= igb_mac_min) in em_sysctl_interrupt_rate_handler()
4870 reg = E1000_READ_REG(hw, E1000_EITR(tque->me)); in em_sysctl_interrupt_rate_handler()
4871 else if (hw->mac.type == e1000_82574 && tque->msix) in em_sysctl_interrupt_rate_handler()
4872 reg = E1000_READ_REG(hw, E1000_EITR_82574(tque->me)); in em_sysctl_interrupt_rate_handler()
4876 rque = oidp->oid_arg1; in em_sysctl_interrupt_rate_handler()
4877 hw = &rque->sc->hw; in em_sysctl_interrupt_rate_handler()
4878 if (hw->mac.type >= igb_mac_min) in em_sysctl_interrupt_rate_handler()
4879 reg = E1000_READ_REG(hw, E1000_EITR(rque->msix)); in em_sysctl_interrupt_rate_handler()
4880 else if (hw->mac.type == e1000_82574 && rque->msix) in em_sysctl_interrupt_rate_handler()
4882 E1000_EITR_82574(rque->msix)); in em_sysctl_interrupt_rate_handler()
4887 if (hw->mac.type < igb_mac_min) { in em_sysctl_interrupt_rate_handler()
4901 if (error || !req->newptr) in em_sysctl_interrupt_rate_handler()
4912 device_t dev = iflib_get_dev(sc->ctx); in em_add_hw_stats()
4913 struct em_tx_queue *tx_que = sc->tx_queues; in em_add_hw_stats()
4914 struct em_rx_queue *rx_que = sc->rx_queues; in em_add_hw_stats()
4919 struct e1000_hw_stats *stats = &sc->stats; in em_add_hw_stats()
4929 CTLFLAG_RD, &sc->dropped_pkts, in em_add_hw_stats()
4932 CTLFLAG_RD, &sc->link_irq, in em_add_hw_stats()
4933 "Link MSI-X IRQ Handled"); in em_add_hw_stats()
4935 CTLFLAG_RD, &sc->rx_overruns, in em_add_hw_stats()
4938 CTLFLAG_RD, &sc->watchdog_events, in em_add_hw_stats()
4949 CTLFLAG_RD, &sc->hw.fc.high_water, 0, in em_add_hw_stats()
4952 CTLFLAG_RD, &sc->hw.fc.low_water, 0, in em_add_hw_stats()
4955 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { in em_add_hw_stats()
4956 struct tx_ring *txr = &tx_que->txr; in em_add_hw_stats()
4969 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", in em_add_hw_stats()
4973 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", in em_add_hw_stats()
4976 CTLFLAG_RD, &txr->tx_irq, in em_add_hw_stats()
4977 "Queue MSI-X Transmit Interrupts"); in em_add_hw_stats()
4980 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) { in em_add_hw_stats()
4981 struct rx_ring *rxr = &rx_que->rxr; in em_add_hw_stats()
4994 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", in em_add_hw_stats()
4998 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", in em_add_hw_stats()
5001 CTLFLAG_RD, &rxr->rx_irq, in em_add_hw_stats()
5002 "Queue MSI-X Receive Interrupts"); in em_add_hw_stats()
5005 /* MAC stats get their own sub node */ in em_add_hw_stats()
5011 CTLFLAG_RD, &stats->ecol, in em_add_hw_stats()
5014 CTLFLAG_RD, &stats->scc, in em_add_hw_stats()
5017 CTLFLAG_RD, &stats->mcc, in em_add_hw_stats()
5020 CTLFLAG_RD, &stats->latecol, in em_add_hw_stats()
5023 CTLFLAG_RD, &stats->colc, in em_add_hw_stats()
5026 CTLFLAG_RD, &sc->stats.symerrs, in em_add_hw_stats()
5029 CTLFLAG_RD, &sc->stats.sec, in em_add_hw_stats()
5032 CTLFLAG_RD, &sc->stats.dc, in em_add_hw_stats()
5035 CTLFLAG_RD, &sc->stats.mpc, in em_add_hw_stats()
5038 CTLFLAG_RD, &sc->stats.rlec, in em_add_hw_stats()
5041 CTLFLAG_RD, &sc->stats.rnbc, in em_add_hw_stats()
5044 CTLFLAG_RD, &sc->stats.ruc, in em_add_hw_stats()
5047 CTLFLAG_RD, &sc->stats.rfc, in em_add_hw_stats()
5050 CTLFLAG_RD, &sc->stats.roc, in em_add_hw_stats()
5053 CTLFLAG_RD, &sc->stats.rjc, in em_add_hw_stats()
5056 CTLFLAG_RD, &sc->stats.rxerrc, in em_add_hw_stats()
5059 CTLFLAG_RD, &sc->stats.crcerrs, in em_add_hw_stats()
5062 CTLFLAG_RD, &sc->stats.algnerrc, in em_add_hw_stats()
5066 CTLFLAG_RD, &sc->stats.cexterr, in em_add_hw_stats()
5069 CTLFLAG_RD, &sc->stats.xonrxc, in em_add_hw_stats()
5072 CTLFLAG_RD, &sc->stats.xontxc, in em_add_hw_stats()
5075 CTLFLAG_RD, &sc->stats.xoffrxc, in em_add_hw_stats()
5078 CTLFLAG_RD, &sc->stats.xofftxc, in em_add_hw_stats()
5081 CTLFLAG_RD, &sc->stats.fcruc, in em_add_hw_stats()
5084 CTLFLAG_RD, &sc->stats.mgprc, in em_add_hw_stats()
5087 CTLFLAG_RD, &sc->stats.mgpdc, in em_add_hw_stats()
5090 CTLFLAG_RD, &sc->stats.mgptc, in em_add_hw_stats()
5095 CTLFLAG_RD, &sc->stats.tpr, in em_add_hw_stats()
5098 CTLFLAG_RD, &sc->stats.gprc, in em_add_hw_stats()
5101 CTLFLAG_RD, &sc->stats.bprc, in em_add_hw_stats()
5104 CTLFLAG_RD, &sc->stats.mprc, in em_add_hw_stats()
5107 CTLFLAG_RD, &sc->stats.prc64, in em_add_hw_stats()
5110 CTLFLAG_RD, &sc->stats.prc127, in em_add_hw_stats()
5111 "65-127 byte frames received"); in em_add_hw_stats()
5113 CTLFLAG_RD, &sc->stats.prc255, in em_add_hw_stats()
5114 "128-255 byte frames received"); in em_add_hw_stats()
5116 CTLFLAG_RD, &sc->stats.prc511, in em_add_hw_stats()
5117 "256-511 byte frames received"); in em_add_hw_stats()
5119 CTLFLAG_RD, &sc->stats.prc1023, in em_add_hw_stats()
5120 "512-1023 byte frames received"); in em_add_hw_stats()
5122 CTLFLAG_RD, &sc->stats.prc1522, in em_add_hw_stats()
5123 "1023-1522 byte frames received"); in em_add_hw_stats()
5125 CTLFLAG_RD, &sc->stats.gorc, in em_add_hw_stats()
5130 CTLFLAG_RD, &sc->stats.gotc, in em_add_hw_stats()
5133 CTLFLAG_RD, &sc->stats.tpt, in em_add_hw_stats()
5136 CTLFLAG_RD, &sc->stats.gptc, in em_add_hw_stats()
5139 CTLFLAG_RD, &sc->stats.bptc, in em_add_hw_stats()
5142 CTLFLAG_RD, &sc->stats.mptc, in em_add_hw_stats()
5145 CTLFLAG_RD, &sc->stats.ptc64, in em_add_hw_stats()
5148 CTLFLAG_RD, &sc->stats.ptc127, in em_add_hw_stats()
5149 "65-127 byte frames transmitted"); in em_add_hw_stats()
5151 CTLFLAG_RD, &sc->stats.ptc255, in em_add_hw_stats()
5152 "128-255 byte frames transmitted"); in em_add_hw_stats()
5154 CTLFLAG_RD, &sc->stats.ptc511, in em_add_hw_stats()
5155 "256-511 byte frames transmitted"); in em_add_hw_stats()
5157 CTLFLAG_RD, &sc->stats.ptc1023, in em_add_hw_stats()
5158 "512-1023 byte frames transmitted"); in em_add_hw_stats()
5160 CTLFLAG_RD, &sc->stats.ptc1522, in em_add_hw_stats()
5161 "1024-1522 byte frames transmitted"); in em_add_hw_stats()
5163 CTLFLAG_RD, &sc->stats.tsctc, in em_add_hw_stats()
5166 CTLFLAG_RD, &sc->stats.tsctfc, in em_add_hw_stats()
5175 CTLFLAG_RD, &sc->stats.iac, in em_add_hw_stats()
5179 CTLFLAG_RD, &sc->stats.icrxptc, in em_add_hw_stats()
5183 CTLFLAG_RD, &sc->stats.icrxatc, in em_add_hw_stats()
5187 CTLFLAG_RD, &sc->stats.ictxptc, in em_add_hw_stats()
5191 CTLFLAG_RD, &sc->stats.ictxatc, in em_add_hw_stats()
5195 CTLFLAG_RD, &sc->stats.ictxqec, in em_add_hw_stats()
5199 CTLFLAG_RD, &sc->stats.ictxqmtc, in em_add_hw_stats()
5203 CTLFLAG_RD, &sc->stats.icrxdmtc, in em_add_hw_stats()
5207 CTLFLAG_RD, &sc->stats.icrxoc, in em_add_hw_stats()
5215 struct e1000_hw *hw = &sc->hw; in em_fw_version_locked()
5216 struct e1000_fw_version *fw_ver = &sc->fw_ver; in em_fw_version_locked()
5228 if (hw->mac.type >= igb_mac_min) { in em_fw_version_locked()
5243 fw_ver->eep_major = (eep & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT; in em_fw_version_locked()
5244 fw_ver->eep_minor = (eep & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT; in em_fw_version_locked()
5245 fw_ver->eep_build = (eep & NVM_IMAGE_ID_MASK); in em_fw_version_locked()
5254 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) { in em_sbuf_fw_version()
5255 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major, in em_sbuf_fw_version()
5256 fw_ver->eep_minor, fw_ver->eep_build); in em_sbuf_fw_version()
5260 if (fw_ver->invm_major || fw_ver->invm_minor || in em_sbuf_fw_version()
5261 fw_ver->invm_img_type) { in em_sbuf_fw_version()
5263 space, fw_ver->invm_major, fw_ver->invm_minor, in em_sbuf_fw_version()
5264 fw_ver->invm_img_type); in em_sbuf_fw_version()
5268 if (fw_ver->or_valid) { in em_sbuf_fw_version()
5269 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", in em_sbuf_fw_version()
5270 space, fw_ver->or_major, fw_ver->or_build, in em_sbuf_fw_version()
5271 fw_ver->or_patch); in em_sbuf_fw_version()
5275 if (fw_ver->etrack_id) in em_sbuf_fw_version()
5276 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id); in em_sbuf_fw_version()
5282 device_t dev = sc->dev; in em_print_fw_version()
5292 em_sbuf_fw_version(&sc->fw_ver, buf); in em_print_fw_version()
5307 device_t dev = sc->dev; in em_sysctl_print_fw_version()
5317 em_sbuf_fw_version(&sc->fw_ver, buf); in em_sysctl_print_fw_version()
5342 result = -1; in em_sysctl_nvm_info()
5345 if (error || !req->newptr) in em_sysctl_nvm_info()
5350 * first 32 16-bit words of the EEPROM to in em_sysctl_nvm_info()
5362 struct e1000_hw *hw = &sc->hw; in em_print_nvm_info()
5363 struct sx *iflib_ctx_lock = iflib_ctx_lock_get(sc->ctx); in em_print_nvm_info()
5395 usecs = info->value; in em_sysctl_int_delay()
5397 if (error != 0 || req->newptr == NULL) in em_sysctl_int_delay()
5401 info->value = usecs; in em_sysctl_int_delay()
5404 sc = info->sc; in em_sysctl_int_delay()
5406 regval = E1000_READ_OFFSET(&sc->hw, info->offset); in em_sysctl_int_delay()
5409 switch (info->offset) { in em_sysctl_int_delay()
5414 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; in em_sysctl_int_delay()
5418 sc->txd_cmd |= E1000_TXD_CMD_IDE; in em_sysctl_int_delay()
5421 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); in em_sysctl_int_delay()
5432 sc = oidp->oid_arg1; in em_sysctl_tso_tcp_flags_mask()
5433 switch (oidp->oid_arg2) { in em_sysctl_tso_tcp_flags_mask()
5450 val = E1000_READ_REG(&sc->hw, reg); in em_sysctl_tso_tcp_flags_mask()
5453 if (error != 0 || req->newptr == NULL) in em_sysctl_tso_tcp_flags_mask()
5458 E1000_WRITE_REG(&sc->hw, reg, val); in em_sysctl_tso_tcp_flags_mask()
5467 info->sc = sc; in em_add_int_delay_sysctl()
5468 info->offset = offset; in em_add_int_delay_sysctl()
5469 info->value = value; in em_add_int_delay_sysctl()
5470 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), in em_add_int_delay_sysctl()
5471 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), in em_add_int_delay_sysctl()
5479 * 0 - off
5480 * 1 - rx pause
5481 * 2 - tx pause
5482 * 3 - full
5493 if ((error) || (req->newptr == NULL)) in em_set_flowcntl()
5496 if (input == sc->fc) /* no change? */ in em_set_flowcntl()
5504 sc->hw.fc.requested_mode = input; in em_set_flowcntl()
5505 sc->fc = input; in em_set_flowcntl()
5512 sc->hw.fc.current_mode = sc->hw.fc.requested_mode; in em_set_flowcntl()
5513 e1000_force_mac_fc(&sc->hw); in em_set_flowcntl()
5520 * 0/1 - off/on
5522 * 250,500,1000-10000 in thousands
5530 error = sysctl_handle_int(oidp, &sc->dmac, 0, req); in igb_sysctl_dmac()
5532 if ((error) || (req->newptr == NULL)) in igb_sysctl_dmac()
5535 switch (sc->dmac) { in igb_sysctl_dmac()
5540 sc->dmac = 1000; in igb_sysctl_dmac()
5554 /* Legal values - allow */ in igb_sysctl_dmac()
5558 sc->dmac = 0; in igb_sysctl_dmac()
5562 em_if_init(sc->ctx); in igb_sysctl_dmac()
5569 * 0/1 - enabled/disabled
5577 if (sc->hw.mac.type < igb_mac_min) in em_sysctl_eee()
5578 value = sc->hw.dev_spec.ich8lan.eee_disable; in em_sysctl_eee()
5580 value = sc->hw.dev_spec._82575.eee_disable; in em_sysctl_eee()
5582 if (error || req->newptr == NULL) in em_sysctl_eee()
5584 if (sc->hw.mac.type < igb_mac_min) in em_sysctl_eee()
5585 sc->hw.dev_spec.ich8lan.eee_disable = (value != 0); in em_sysctl_eee()
5587 sc->hw.dev_spec._82575.eee_disable = (value != 0); in em_sysctl_eee()
5588 em_if_init(sc->ctx); in em_sysctl_eee()
5600 result = -1; in em_sysctl_debug_info()
5603 if (error || !req->newptr) in em_sysctl_debug_info()
5624 if (error || !req->newptr || result != 1) in em_get_rs()
5639 * needed for debugging a problem. -jfv
5644 device_t dev = iflib_get_dev(sc->ctx); in em_print_debug_info()
5645 if_t ifp = iflib_get_ifp(sc->ctx); in em_print_debug_info()
5646 struct tx_ring *txr = &sc->tx_queues->txr; in em_print_debug_info()
5647 struct rx_ring *rxr = &sc->rx_queues->rxr; in em_print_debug_info()
5659 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { in em_print_debug_info()
5660 device_printf(dev, "TX Queue %d ------\n", i); in em_print_debug_info()
5662 E1000_READ_REG(&sc->hw, E1000_TDH(i)), in em_print_debug_info()
5663 E1000_READ_REG(&sc->hw, E1000_TDT(i))); in em_print_debug_info()
5666 for (int j=0; j < sc->rx_num_queues; j++, rxr++) { in em_print_debug_info()
5667 device_printf(dev, "RX Queue %d ------\n", j); in em_print_debug_info()
5669 E1000_READ_REG(&sc->hw, E1000_RDH(j)), in em_print_debug_info()
5670 E1000_READ_REG(&sc->hw, E1000_RDT(j))); in em_print_debug_info()
5676 * Write a new value to the EEPROM increasing the number of MSI-X
5683 struct e1000_hw *hw = &sc->hw; in em_enable_vectors_82574()
5692 "reported MSI-X vectors from 3 to 5...\n"); in em_enable_vectors_82574()