| /linux/arch/m68k/include/uapi/asm/ |
| H A D | bootinfo-mac.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 ** asm/bootinfo-mac.h -- Macintosh-specific boot information definitions
11 * Macintosh-specific tags (all __be32)
14 #define BI_MAC_MODEL 0x8000 /* Mac Gestalt ID (model type) */
15 #define BI_MAC_VADDR 0x8001 /* Mac video base address */
16 #define BI_MAC_VDEPTH 0x8002 /* Mac video depth */
17 #define BI_MAC_VROW 0x8003 /* Mac video rowbytes */
18 #define BI_MAC_VDIM 0x8004 /* Mac video dimensions */
19 #define BI_MAC_VLOGICAL 0x8005 /* Mac video logical base */
20 #define BI_MAC_SCCBASE 0x8006 /* Mac SCC base address */
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| /linux/drivers/net/ethernet/mellanox/mlxbf_gige/ |
| H A D | mlxbf_gige_rx.c | 1 // SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
5 * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES
16 void __iomem *base = priv->base; in mlxbf_gige_enable_multicast_rx() local
19 data = readq(base + MLXBF_GIGE_RX_MAC_FILTER_GENERAL); in mlxbf_gige_enable_multicast_rx()
21 writeq(data, base + MLXBF_GIGE_RX_MAC_FILTER_GENERAL); in mlxbf_gige_enable_multicast_rx()
26 void __iomem *base = priv->base; in mlxbf_gige_disable_multicast_rx() local
29 data = readq(base + MLXBF_GIGE_RX_MAC_FILTER_GENERAL); in mlxbf_gige_disable_multicast_rx()
31 writeq(data, base + MLXBF_GIGE_RX_MAC_FILTER_GENERAL); in mlxbf_gige_disable_multicast_rx()
37 void __iomem *base = priv->base; in mlxbf_gige_enable_mac_rx_filter() local
40 /* Enable MAC receive filter mask for specified index */ in mlxbf_gige_enable_mac_rx_filter()
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| H A D | mlxbf_gige_main.c | 1 // SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
5 * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES
10 #include <linux/dma-mapping.h>
41 skb = netdev_alloc_skb(priv->netdev, MLXBF_GIGE_DEFAULT_BUF_SZ * 2); in mlxbf_gige_alloc_skb()
45 /* Adjust the headroom so that skb->data is naturally aligned to in mlxbf_gige_alloc_skb()
48 addr = (long)skb->data; in mlxbf_gige_alloc_skb()
49 offset = (addr + MLXBF_GIGE_DEFAULT_BUF_SZ - 1) & in mlxbf_gige_alloc_skb()
50 ~(MLXBF_GIGE_DEFAULT_BUF_SZ - 1); in mlxbf_gige_alloc_skb()
51 offset -= addr; in mlxbf_gige_alloc_skb()
56 *buf_dma = dma_map_single(priv->dev, skb->data, map_len, dir); in mlxbf_gige_alloc_skb()
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| /linux/drivers/net/ethernet/qualcomm/emac/ |
| H A D | emac-mac.c | 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
5 /* Qualcomm Technologies, Inc. EMAC Ethernet Controller MAC layer support
18 #include "emac-sgmii.h"
210 #define EMAC_SKB_CB(skb) ((struct emac_skb_cb *)(skb)->cb)
234 #define EMAC_RRD(RXQ, SIZE, IDX) ((RXQ)->rrd.v_addr + (SIZE * (IDX)))
235 #define EMAC_RFD(RXQ, SIZE, IDX) ((RXQ)->rfd.v_addr + (SIZE * (IDX)))
236 #define EMAC_TPD(TXQ, SIZE, IDX) ((TXQ)->tpd.v_addr + (SIZE * (IDX)))
238 #define GET_RFD_BUFFER(RXQ, IDX) (&((RXQ)->rfd.rfbuff[(IDX)]))
239 #define GET_TPD_BUFFER(RTQ, IDX) (&((RTQ)->tpd.tpbuff[(IDX)]))
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| /linux/drivers/net/ethernet/faraday/ |
| H A D | ftgmac100.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * (C) Copyright 2009-2011 Faraday Technology
6 * Po-Yu Chuang <ratbert@faraday-tech.com>
13 #include <linux/dma-mapping.h>
55 /* For NC-SI to register a fixed-link phy device */
67 void __iomem *base; member
129 struct net_device *netdev = priv->netdev; in ftgmac100_reset_mac()
133 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); in ftgmac100_reset_mac()
135 priv->base + FTGMAC100_OFFSET_MACCR); in ftgmac100_reset_mac()
139 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); in ftgmac100_reset_mac()
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| /linux/Documentation/networking/ |
| H A D | oa-tc6-framework.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
4 OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface (TC6) Framework Support
8 ------------
11 single pair of conductors. The 10BASE-T1L (Clause 146) is a long reach
12 PHY supporting full duplex point-to-point operation over 1 km of single
13 balanced pair of conductors. The 10BASE-T1S (Clause 147) is a short reach
14 PHY supporting full / half duplex point-to-point operation over 15 m of
21 works in conjunction with the 10BASE-T1S PHY operating in multidrop mode.
23 The aforementioned PHYs are intended to cover the low-speed / low-cost
29 The MAC-PHY solution integrates an IEEE Clause 4 MAC and a 10BASE-T1x PHY
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| /linux/Documentation/devicetree/bindings/net/ |
| H A D | microchip,lan8650.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip LAN8650/1 10BASE-T1S MACPHY Ethernet Controllers
10 - Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
13 The LAN8650/1 combines a Media Access Controller (MAC) and an Ethernet
14 PHY to enable 10BASE‑T1S networks. The Ethernet Media Access Controller
15 (MAC) module implements a 10 Mbps half duplex Ethernet MAC, compatible
16 with the IEEE 802.3 standard and a 10BASE-T1S physical layer transceiver
18 the MAC-PHY is specified in the OPEN Alliance 10BASE-T1x MACPHY Serial
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| H A D | hisilicon-hns-dsaf.txt | 4 - compatible: should be "hisilicon,hns-dsaf-v1" or "hisilicon,hns-dsaf-v2".
5 "hisilicon,hns-dsaf-v1" is for hip05.
6 "hisilicon,hns-dsaf-v2" is for Hi1610 and Hi1612.
7 - mode: dsa fabric mode string. only support one of dsaf modes like these:
8 "2port-64vf",
9 "6port-16rss",
10 "6port-16vf",
11 "single-port".
12 - interrupts: should contain the DSA Fabric and rcb interrupt.
13 - reg: specifies base physical address(es) and size of the device registers.
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| H A D | hisilicon-femac.txt | 1 Hisilicon Fast Ethernet MAC controller
4 - compatible: should contain one of the following version strings:
5 * "hisilicon,hisi-femac-v1"
6 * "hisilicon,hisi-femac-v2"
7 and the soc string "hisilicon,hi3516cv300-femac".
8 - reg: specifies base physical address(s) and size of the device registers.
9 The first region is the MAC core register base and size.
10 The second region is the global MAC control register.
11 - interrupts: should contain the MAC interrupt.
12 - clocks: A phandle to the MAC main clock.
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| H A D | cpsw.txt | 2 ------------------------------------------------------
5 - compatible : Should be one of the below:-
7 "ti,am335x-cpsw" for AM335x controllers
8 "ti,am4372-cpsw" for AM437x controllers
9 "ti,dra7-cpsw" for DRA7x controllers
10 - reg : physical base address and size of the cpsw
12 - interrupts : property with a value describing the interrupt
14 - cpdma_channels : Specifies number of channels in CPDMA
15 - ale_entries : Specifies No of entries ALE can hold
16 - bd_ram_size : Specifies internal descriptor RAM size
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| H A D | ti,dp83869.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
21 This device interfaces to the MAC layer through Reduced GMII (RGMII) and
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| H A D | adi,adin1110.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ADI ADIN1110 MAC-PHY
10 - Marcelo Schmitt <marcelo.schmitt@analog.com>
13 The ADIN1110 is a low power single port 10BASE-T1L MAC-
15 an Ethernet PHY core with a MAC and all the associated analog
18 The ADIN2111 is a low power, low complexity, two-Ethernet ports
19 switch with integrated 10BASE-T1L PHYs and one serial peripheral
22 with the IEEE 802.3cg-2019 Ethernet standard for long reach
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| H A D | hisilicon-hix5hd2-gmac.txt | 4 - compatible: should contain one of the following SoC strings:
5 * "hisilicon,hix5hd2-gmac"
6 * "hisilicon,hi3798cv200-gmac"
7 * "hisilicon,hi3516a-gmac"
9 * "hisilicon,hisi-gmac-v1"
10 * "hisilicon,hisi-gmac-v2"
13 - reg: specifies base physical address(s) and size of the device registers.
14 The first region is the MAC register base and size.
16 - interrupts: should contain the MAC interrupt.
17 - #address-cells: must be <1>.
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| /linux/drivers/net/ethernet/amd/ |
| H A D | au1000_eth.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright 2001-2003, 2006 MontaVista Software Inc.
8 * Added ethtool/mii-tool support,
11 * or riemer@riemer-nt.de: fixed the link beat detection with
14 * converted to use linux-2.6.x's PHY framework
22 #include <linux/dma-mapping.h>
67 #define DRV_DESC "Au1xxx on-chip Ethernet driver"
73 /* AU1000 MAC registers and bits */
202 * make sure there's no out-of-order writes, and that all writes
207 * board-specific configurations
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| /linux/drivers/net/ethernet/rdc/ |
| H A D | r6040.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * RDC R6040 Fast Ethernet MAC support
7 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
8 * Copyright (C) 2007-2012 Florian Fainelli <f.fainelli@gmail.com>
43 /* RDC MAC I/O Size */
46 /* MAX RDC MAC */
49 /* MAC registers */
57 #define MAC_RST 0x0001 /* Reset the MAC */
62 #define TM2TX 0x0001 /* Trigger MAC to transmit */
66 #define TX_FIFO_UNDR 0x0200 /* TX FIFO under-run */
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| /linux/Documentation/networking/dsa/ |
| H A D | sja1105.rst | 8 The NXP SJA1105 is a family of 10 SPI-managed automotive switches:
10 - SJA1105E: First generation, no TTEthernet
11 - SJA1105T: First generation, TTEthernet
12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
16 - SJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and
17 100base-TX PHYs
18 - SJA1110B: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
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| /linux/Documentation/devicetree/bindings/nvmem/layouts/ |
| H A D | fixed-cell.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/layouts/fixed-cell.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rafał Miłecki <rafal@milecki.pl>
11 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
16 - const: mac-base
18 Cell with base MAC address to be used for calculating extra relative
27 $ref: /schemas/types.yaml#/definitions/uint32-array
29 - minimum: 0
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| H A D | fixed-layout.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/layouts/fixed-layout.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
17 - Rafał Miłecki <rafal@milecki.pl>
21 const: fixed-layout
23 "#address-cells":
26 "#size-cells":
30 "@[a-f0-9]+(,[0-7])?$":
32 $ref: fixed-cell.yaml
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| /linux/drivers/net/ethernet/freescale/ |
| H A D | gianfar.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
16 * -Add support for module parameters
17 * -Add patch for ethtool phys id
67 #define DRV_NAME "gfar-enet"
92 #define GFAR_RXB_SIZE rounddown(GFAR_RXB_TRUESIZE - GFAR_SKBFRAG_OVR, 64)
95 #define TX_RING_MOD_MASK(size) (size-1)
96 #define RX_RING_MOD_MASK(size) (size-1)
135 /* MAC register bits */
281 /* weighted round-robin scheduling (WRRS) */
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| /linux/drivers/net/ethernet/intel/e1000e/ |
| H A D | ethtool.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
28 "s0ix-enabled",
36 .sizeof_stat = sizeof(((struct e1000_adapter *)0)->m), \
41 .sizeof_stat = sizeof(((struct rtnl_link_stats64 *)0)->m), \
115 struct e1000_hw *hw = &adapter->hw; in e1000_get_link_ksettings()
117 if (hw->phy.media_type == e1000_media_type_copper) { in e1000_get_link_ksettings()
127 if (hw->phy.type == e1000_phy_ife) in e1000_get_link_ksettings()
131 if (hw->mac.autoneg == 1) { in e1000_get_link_ksettings()
134 advertising |= hw->phy.autoneg_advertised; in e1000_get_link_ksettings()
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| /linux/drivers/net/ethernet/oki-semi/pch_gbe/ |
| H A D | pch_gbe_ethtool.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 1999 - 2010 Intel Corporation.
14 * pch_gbe_stats - Stats item information
30 * pch_gbe_gstrings_stats - ethtool information status name list
67 * pch_gbe_get_link_ksettings - Get device-specific settings
80 mii_ethtool_get_link_ksettings(&adapter->mii, ecmd); in pch_gbe_get_link_ksettings()
83 ecmd->link_modes.supported); in pch_gbe_get_link_ksettings()
85 ecmd->link_modes.advertising); in pch_gbe_get_link_ksettings()
90 ethtool_convert_legacy_u32_to_link_mode(ecmd->link_modes.supported, in pch_gbe_get_link_ksettings()
92 ethtool_convert_legacy_u32_to_link_mode(ecmd->link_modes.advertising, in pch_gbe_get_link_ksettings()
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| /linux/drivers/net/ethernet/nvidia/ |
| H A D | forcedeth.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * engineered documentation written by Carl-Daniel Hailfinger
15 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
50 #include <linux/dma-mapping.h>
73 #define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
82 #define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */
466 /* rx/tx mac addr + type + vlan + align + slack*/
483 * - DESC_VER_1: Original
484 * - DESC_VER_2: support for jumbo frames.
485 * - DESC_VER_3: 64-bit format.
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| /linux/drivers/net/ethernet/ezchip/ |
| H A D | nps_enet.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
59 /* Gbps Eth MAC Configuration 0 register masks and shifts */
93 /* Gbps Eth MAC Configuration 1 register masks and shifts */
103 /* Gbps Eth MAC Configuration 2 register masks and shifts */
119 /* Gbps Eth MAC Configuration 3 register masks and shifts */
141 /* GE MAC, PCS reset control register masks and shifts */
154 * struct nps_enet_priv - Storage of ENET's private information.
155 * @regs_base: Base address of ENET memory-mapped control registers.
170 * nps_enet_reg_set - Sets ENET register with provided value.
172 * @reg: Register offset from base address.
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| /linux/drivers/net/ethernet/sun/ |
| H A D | sungem.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
39 * This auto-clearing does not occur when the alias at GREG_STAT2
52 #define GREG_STAT_TXMAC 0x00004000 /* TX MAC signalled interrupt */
53 #define GREG_STAT_RXMAC 0x00008000 /* RX MAC signalled interrupt */
54 #define GREG_STAT_MAC 0x00010000 /* MAC Control signalled irq */
69 * signalled to the cpu. GREG_IACK can be used to clear specific top-level
110 #define TXDMA_DBLOW 0x2008UL /* TX Desc. Base Low */
111 #define TXDMA_DBHI 0x200CUL /* TX Desc. Base High */
130 * This 13-bit register is programmed by the driver to hold the descriptor
136 * This 13-bit register is updated by GEM to hold to descriptor entry index
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| /linux/drivers/net/dsa/hirschmann/ |
| H A D | hellcreek.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 * Copyright (C) 2019-2021 Linutronix GmbH
97 return readw(hellcreek->base + offset); in hellcreek_read()
102 return readw(hellcreek->base + HR_CTRL_C); in hellcreek_read_ctrl()
107 return readw(hellcreek->base + HR_SWSTAT); in hellcreek_read_stat()
113 writew(data, hellcreek->base + offset); in hellcreek_write()
213 if (id != hellcreek->pdata->module_id) in hellcreek_detect()
214 return -ENODEV; in hellcreek_detect()
221 dev_info(hellcreek->dev, "Module ID=%02x Release=%04x Date=%04x TGD Version=%02x.%02x\n", in hellcreek_detect()
236 hellcreek->fdb_entries = ((features & HR_FEABITS0_FDBBINS_MASK) >> in hellcreek_feature_detect()
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