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/freebsd/sys/dev/clk/allwinner/
H A Dccu_a10.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
47 #include <dt-bindings/clock/sun4i-a10-ccu.h>
48 #include <dt-bindings/clock/sun7i-a20-ccu.h>
49 #include <dt-bindings/reset/sun4i-a10-ccu.h>
51 /* Non-exported resets */
52 /* Non-exported clocks */
66 /* Non-exported fixed clocks */
106 CCU_GATE(CLK_AHB_OTG, "ahb-otg", "ahb", 0x60, 0)
107 CCU_GATE(CLK_AHB_EHCI0, "ahb-ehci0", "ahb", 0x60, 1)
[all …]
H A Dccu_a13.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
47 #include <dt-bindings/clock/sun5i-ccu.h>
48 #include <dt-bindings/reset/sun5i-ccu.h>
50 /* Non-exported clocks */
101 CCU_GATE(CLK_DRAM_AXI, "axi-dram", "axi", 0x5c, 0)
103 CCU_GATE(CLK_AHB_OTG, "ahb-otg", "ahb", 0x60, 0)
104 CCU_GATE(CLK_AHB_EHCI, "ahb-ehci", "ahb", 0x60, 1)
105 CCU_GATE(CLK_AHB_OHCI, "ahb-ohci", "ahb", 0x60, 2)
106 CCU_GATE(CLK_AHB_SS, "ahb-ss", "ahb", 0x60, 5)
[all …]
H A Dccu_d1.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
52 #include <dt-bindings/clock/sun20i-d1-ccu.h>
53 #include <dt-bindings/reset/sun20i-d1-ccu.h>
125 CCU_GATE(CLK_BUS_DE, "bus-de", "psi-ahb", 0x60C, 0)
126 CCU_GATE(CLK_BUS_DI, "bus-di", "psi-ahb", 0x62C, 0)
127 CCU_GATE(CLK_BUS_G2D, "bus-g2d", "psi-ahb", 0x63C, 0)
128 CCU_GATE(CLK_BUS_CE, "bus-ce", "psi-ahb", 0x68C, 0)
129 CCU_GATE(CLK_BUS_VE, "bus-ve", "psi-ahb", 0x690, 0)
130 CCU_GATE(CLK_BUS_DMA, "bus-dma", "psi-ahb", 0x70C, 0)
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/qcom/
H A Dqcom,geni-se.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#
5 $schema: http://devicetree.org/meta-schema
[all...]
/freebsd/sys/contrib/device-tree/Bindings/arm/stm32/
H A Dst,mlahb.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 ML-AHB interconnect
10 - Fabien Dessenne <fabien.dessenne@foss.st.com>
11 - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
14 These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects
15 a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory
17 using different buses (see [2]): balancing the Cortex-M firmware accesses
23 - $ref: /schemas/simple-bus.yaml#
[all …]
/freebsd/sys/arm/allwinner/
H A Dif_awg.c1 /*-
71 #define RD4(sc, reg) bus_read_4((sc)->res[_RES_EMAC], (reg))
72 #define WR4(sc, reg, val) bus_write_4((sc)->res[_RES_EMAC], (reg), (val))
74 #define AWG_LOCK(sc) mtx_lock(&(sc)->mtx)
75 #define AWG_UNLOCK(sc) mtx_unlock(&(sc)->mtx);
76 #define AWG_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
77 #define AWG_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED)
86 #define TX_NEXT(n) (((n) + 1) & (TX_DESC_COUNT - 1))
87 #define TX_SKIP(n, o) (((n) + (o)) & (TX_DESC_COUNT - 1))
88 #define RX_NEXT(n) (((n) + 1) & (RX_DESC_COUNT - 1))
[all …]
/freebsd/sys/contrib/device-tree/src/arm/allwinner/
H A Dsun9i-a80.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
48 #include <dt-bindings/clock/sun9i-a80-de.h>
49 #include <dt-bindings/clock/sun9i-a80-usb.h>
50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
51 #include <dt-bindings/reset/sun9i-a80-de.h>
52 #include <dt-bindings/reset/sun9i-a80-usb.h>
[all …]
H A Dsuniv-f1c100s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
7 #include <dt-bindings/clock/suniv-ccu-f1c100s.h>
8 #include <dt-bindings/reset/suniv-ccu-f1c100s.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&intc>;
16 osc24M: clk-24M {
17 #clock-cells = <0>;
18 compatible = "fixed-clock";
19 clock-frequency = <24000000>;
[all …]
H A Dsun5i.dtsi2 * Copyright 2012-2015 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/clock/sun5i-ccu.h>
46 #include <dt-bindings/dma/sun4i-a10.h>
47 #include <dt-bindings/reset/sun5i-ccu.h>
50 interrupt-parent = <&intc>;
51 #address-cells = <1>;
52 #size-cells = <1>;
55 #address-cells = <1>;
[all …]
H A Dsun6i-a31.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
48 #include <dt-bindings/clock/sun6i-a31-ccu.h>
49 #include <dt-bindings/clock/sun6i-rtc.h>
50 #include <dt-bindings/reset/sun6i-a31-ccu.h>
53 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <1>;
[all …]
H A Dsun4i-a10.dtsi5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/thermal/thermal.h>
45 #include <dt-bindings/dma/sun4i-a10.h>
46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
50 #address-cells = <1>;
51 #size-cells = <1>;
52 interrupt-parent = <&intc>;
59 #address-cells = <1>;
60 #size-cells = <1>;
[all …]
H A Dsun7i-a20.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/dma/sun4i-a10.h>
48 #include <dt-bindings/clock/sun7i-a20-ccu.h>
49 #include <dt-bindings/reset/sun4i-a10-ccu.h>
50 #include <dt-bindings/pinctrl/sun4i-a10.h>
53 interrupt-parent = <&gic>;
54 #address-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/microchip/
H A Dusb_a9260.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * usb_a9260.dts - Device Tree file for Caloa USB A9260 board
5 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 /dts-v1/;
13 compatible = "calao,usb-a9260", "atmel,at91sam9260", "atmel,at91sam9";
16 bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
23 ahb {
26 atmel,wakeup-counter = <10>;
27 atmel,wakeup-rtt-timer;
H A Dtny_a9260_common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * tny_a9260_common.dtsi - Device Tree file for Caloa TNY A926x board
5 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock6 rw rootfstype=ubifs";
19 clock-frequency = <32768>;
23 clock-frequency = <12000000>;
27 ahb {
31 compatible = "atmel,tcb-timer";
36 compatible = "atmel,tcb-timer";
49 nand_controller: nand-controller {
[all …]
H A Dtny_a9263.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * usb_a9263.dts - Device Tree file for Caloa USB A9293 board
5 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 /dts-v1/;
12 compatible = "atmel,tny-a9263", "atmel,at91sam9263", "atmel,at91sam9";
15 bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
24 clock-frequency = <32768>;
28 clock-frequency = <12000000>;
32 ahb {
40 compatible = "atmel,tcb-timer";
[all …]
H A Dusb_a9263.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * usb_a9263.dts - Device Tree file for Caloa USB A9293 board
5 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 /dts-v1/;
12 compatible = "atmel,usb-a9263", "atmel,at91sam9263", "atmel,at91sam9";
15 bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
24 clock-frequency = <32768>;
28 clock-frequency = <12000000>;
32 ahb {
40 compatible = "atmel,tcb-timer";
[all …]
H A Dat91sam9263ek.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91sam9263ek.dts - Device Tree file for Atmel at91sam9263 reference board
5 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 /dts-v1/;
15 bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs";
16 stdout-path = "serial0:115200n8";
25 clock-frequency = <32768>;
29 clock-frequency = <16367660>;
33 ahb {
41 compatible = "atmel,tcb-timer";
[all …]
H A Dat91sam9g20ek_common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91sam9g20ek_common.dtsi - Device Tree file for Atmel at91sam9g20ek board
5 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 #include <dt-bindings/input/input.h>
13 bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs";
14 stdout-path = "serial0:115200n8";
23 clock-frequency = <32768>;
27 clock-frequency = <18432000>;
31 ahb {
50 pinctrl_board_mmc0_slot1: mmc0_slot1-board {
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dste-u300-syscon-clock.txt1 Clock bindings for ST-Ericsson U300 System Controller Clocks
6 - compatible: must be "stericsson,u300-syscon-clk"
7 - #clock-cells: must be <0>
8 - clock-type: specifies the type of clock:
12 - clock-id: specifies the clock in the type range
15 - clocks: parent clock(s)
20 -------------------
40 2 10 AHB Subsystem Bridge clock
45 gpio_clk: gpio_clk@13M {
46 #clock-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Drockchip,i2s-tdm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/rockchip,i2s-tdm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
18 - $ref: dai-common.yaml#
23 - rockchip,px30-i2s-tdm
24 - rockchip,rk1808-i2s-tdm
25 - rockchip,rk3308-i2s-tdm
26 - rockchip,rk3568-i2s-tdm
[all …]
/freebsd/sys/contrib/device-tree/src/riscv/starfive/
H A Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
[all …]
/freebsd/sys/arm64/freescale/imx/
H A Dimx8mq_ccm.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
30 * Clocks driver for Freescale i.MX 8M Quad SoC.
215 COMPOSITE(IMX8MQ_CLK_AHB, "ahb", ahb_p, 0x9000, 0),
216 DIV(IMX8MQ_CLK_IPG_ROOT, "ipg_root", "ahb", 0x9080, 0, 1),
284 sc->dev = dev; in imx8mq_ccm_attach()
286 sc->clks = imx8mq_clks; in imx8mq_ccm_attach()
287 sc->nclks = nitems(imx8mq_clks); in imx8mq_ccm_attach()
299 if (ofw_bus_is_compatible(dev, "fsl,imx8mq-ccm") == 0) in imx8mq_ccm_probe()
302 device_set_desc(dev, "Freescale i.MX 8M Quad Clock Control Module"); in imx8mq_ccm_probe()
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6sll.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright 2017-2018 NXP.
8 #include <dt-bindings/clock/imx6sll-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include "imx6sll-pinfunc.h"
14 #address-cells = <1>;
15 #size-cells = <1>;
46 #address-cells = <1>;
47 #size-cells = <0>;
[all …]
H A Dimxrt1050.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "../../armv7-m.dtsi"
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/imxrt1050-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 clock-frequency = <24000000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mn.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mn-clock.h>
7 #include <dt-bindings/power/imx8mn-power.h>
8 #include <dt-bindings/reset/imx8mq-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mn-pinfunc.h"
17 interrupt-parent = <&gic>;
[all …]

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