1c66ec88fSEmmanuel Vadot# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2c66ec88fSEmmanuel Vadot%YAML 1.2 3c66ec88fSEmmanuel Vadot--- 4aa1a8ff2SEmmanuel Vadot$id: http://devicetree.org/schemas/arm/stm32/st,mlahb.yaml# 5aa1a8ff2SEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 6c66ec88fSEmmanuel Vadot 78bab661aSEmmanuel Vadottitle: STMicroelectronics STM32 ML-AHB interconnect 8c66ec88fSEmmanuel Vadot 9c66ec88fSEmmanuel Vadotmaintainers: 108cc087a1SEmmanuel Vadot - Fabien Dessenne <fabien.dessenne@foss.st.com> 118cc087a1SEmmanuel Vadot - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> 12c66ec88fSEmmanuel Vadot 13c66ec88fSEmmanuel Vadotdescription: | 14c66ec88fSEmmanuel Vadot These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects 15c66ec88fSEmmanuel Vadot a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory 16c66ec88fSEmmanuel Vadot parts can be accessed through different addresses (see "RAM aliases" in [1]) 17c66ec88fSEmmanuel Vadot using different buses (see [2]): balancing the Cortex-M firmware accesses 18c66ec88fSEmmanuel Vadot among those ports allows to tune the system performance. 19c66ec88fSEmmanuel Vadot [1]: https://www.st.com/resource/en/reference_manual/dm00327659.pdf 20c66ec88fSEmmanuel Vadot [2]: https://wiki.st.com/stm32mpu/wiki/STM32MP15_RAM_mapping 21c66ec88fSEmmanuel Vadot 22c66ec88fSEmmanuel VadotallOf: 23c66ec88fSEmmanuel Vadot - $ref: /schemas/simple-bus.yaml# 24c66ec88fSEmmanuel Vadot 25c66ec88fSEmmanuel Vadotproperties: 26c66ec88fSEmmanuel Vadot compatible: 27c66ec88fSEmmanuel Vadot contains: 28c66ec88fSEmmanuel Vadot enum: 29c66ec88fSEmmanuel Vadot - st,mlahb 30c66ec88fSEmmanuel Vadot 31c66ec88fSEmmanuel Vadot dma-ranges: 32c66ec88fSEmmanuel Vadot description: | 33c66ec88fSEmmanuel Vadot Describe memory addresses translation between the local CPU and the 34c66ec88fSEmmanuel Vadot remote Cortex-M processor. Each memory region, is declared with 35c66ec88fSEmmanuel Vadot 3 parameters: 36c66ec88fSEmmanuel Vadot - param 1: device base address (Cortex-M processor address) 37c66ec88fSEmmanuel Vadot - param 2: physical base address (local CPU address) 38c66ec88fSEmmanuel Vadot - param 3: size of the memory region. 39c66ec88fSEmmanuel Vadot maxItems: 3 40c66ec88fSEmmanuel Vadot 41c66ec88fSEmmanuel Vadot '#address-cells': 42c66ec88fSEmmanuel Vadot const: 1 43c66ec88fSEmmanuel Vadot 44c66ec88fSEmmanuel Vadot '#size-cells': 45c66ec88fSEmmanuel Vadot const: 1 46c66ec88fSEmmanuel Vadot 47c66ec88fSEmmanuel Vadotrequired: 48c66ec88fSEmmanuel Vadot - compatible 49c66ec88fSEmmanuel Vadot - '#address-cells' 50c66ec88fSEmmanuel Vadot - '#size-cells' 51c66ec88fSEmmanuel Vadot - dma-ranges 52c66ec88fSEmmanuel Vadot 536be33864SEmmanuel VadotunevaluatedProperties: false 546be33864SEmmanuel Vadot 55c66ec88fSEmmanuel Vadotexamples: 56c66ec88fSEmmanuel Vadot - | 57*7d0873ebSEmmanuel Vadot ahb { 58c66ec88fSEmmanuel Vadot compatible = "st,mlahb", "simple-bus"; 59c66ec88fSEmmanuel Vadot #address-cells = <1>; 60c66ec88fSEmmanuel Vadot #size-cells = <1>; 61c66ec88fSEmmanuel Vadot ranges; 62c66ec88fSEmmanuel Vadot dma-ranges = <0x00000000 0x38000000 0x10000>, 63c66ec88fSEmmanuel Vadot <0x10000000 0x10000000 0x60000>, 64c66ec88fSEmmanuel Vadot <0x30000000 0x30000000 0x60000>; 65c66ec88fSEmmanuel Vadot 66c66ec88fSEmmanuel Vadot m4_rproc: m4@10000000 { 67c66ec88fSEmmanuel Vadot reg = <0x10000000 0x40000>; 68c66ec88fSEmmanuel Vadot }; 69c66ec88fSEmmanuel Vadot }; 70c66ec88fSEmmanuel Vadot 71c66ec88fSEmmanuel Vadot... 72