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Searched +full:lx2160a +full:- +full:pcie (Results 1 – 6 of 6) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dmbvl,gpex40-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mbvl,gpex40-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mobiveil AXI PCIe Host Bridge
10 - Frank Li <Frank Li@nxp.com>
13 Mobiveil's GPEX 4.0 is a PCIe Gen4 host bridge IP. This configurable IP
16 NXP Layerscape PCIe Gen4 controller (Deprecated) base on Mobiveil's GPEX 4.0.
21 - fsl,lx2160a-pcie
22 - mbvl,gpex40-pcie
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H A Dlayerscape-pcie-gen4.txt1 NXP Layerscape PCIe Gen4 controller
3 This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all
4 the common properties defined in mobiveil-pcie.txt.
7 - compatible: should contain the platform identifier such as:
8 "fsl,lx2160a-pcie"
9 - reg: base addresses and lengths of the PCIe controller register blocks.
11 "config_axi_slave": PCIe controller registers
12 - interrupts: A list of interrupt outputs of the controller. Must contain an
13 entry for each entry in the interrupt-names property.
14 - interrupt-names: It could include the following entries:
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H A Dlayerscape-pci.txt1 Freescale Layerscape PCIe controller
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 which is used to describe the PLL settings at the time of chip-reset.
10 register available in the Freescale PCIe controller register set,
11 which can allow determining the underlying DesignWare PCIe controller version
15 - compatible: should contain the platform identifier such as:
17 "fsl,ls1021a-pcie"
18 "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
19 "fsl,ls2088a-pcie"
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-lx2160a.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
15 compatible = "fsl,lx2160a";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
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H A Dfsl-lx2160a-rev2.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
12 compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
15 reg-names = "regs", "config";
21 interrupt-names = "intr";
23 /delete-property/ apio-wins;
24 /delete-property/ ppio-wins;
28 compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
31 reg-names = "regs", "config";
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H A Dfsl-ls1028a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
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