/freebsd/sys/contrib/device-tree/Bindings/display/bridge/ |
H A D | renesas,lvds.txt | 1 Renesas R-Car LVDS Encoder 4 These DT bindings describe the LVDS encoder embedded in the Renesas R-Car 5 Gen2, R-Car Gen3 and RZ/G SoCs. 9 - compatible : Shall contain one of 10 - "renesas,r8a7743-lvds" for R8A7743 (RZ/G1M) compatible LVDS encoders 11 - "renesas,r8a7744-lvds" for R8A7744 (RZ/G1N) compatible LVDS encoders 12 - "renesas,r8a774a1-lvds" for R8A774A1 (RZ/G2M) compatible LVDS encoders 13 - "renesas,r8a774b1-lvds" for R8A774B1 (RZ/G2N) compatible LVDS encoders 14 - "renesas,r8a774c0-lvds" for R8A774C0 (RZ/G2E) compatible LVDS encoders 15 - "renesas,r8a7790-lvds" for R8A7790 (R-Car H2) compatible LVDS encoders [all …]
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H A D | renesas,lvds.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/bridge/renesas,lvds.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Renesas R-Car LVDS Encoder 10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> 13 These DT bindings describe the LVDS encoder embedded in the Renesas R-Car 14 Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs. 19 - renesas,r8a7742-lvds # for RZ/G1H compatible LVDS encoders 20 - renesas,r8a7743-lvds # for RZ/G1M compatible LVDS encoders [all …]
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H A D | lvds-codec.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/display/bridge/lvds-codec.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Transparent LVDS encoders and decoders 10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> 13 This binding supports transparent LVDS encoders and decoders that don't 16 LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple 18 to LVDS panels. This binding targets devices compatible with the following 21 [JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February [all …]
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/freebsd/sys/contrib/device-tree/src/arm/nvidia/ |
H A D | tegra30-asus-lvds-display.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 /* This dtsi file describes parts common for Asus T30 devices with a LVDS panel. */ 5 #include <dt-bindings/gpio/tegra-gpio.h> 15 remote-endpoint = <&bridge_input>; 16 bus-width = <24>; 23 display-panel { 24 power-suppl [all...] |
H A D | tegra20-asus-tf101.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/atmel-maxtouch.h> 5 #include <dt-bindings/input/gpio-keys.h> 6 #include <dt-bindings/input/input.h> 7 #include <dt-binding [all...] |
H A D | tegra20-acer-a500-picasso.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/atmel-maxtouch.h> 5 #include <dt-bindings/input/gpio-keys.h> 6 #include <dt-bindings/input/input.h> 7 #include <dt-binding [all...] |
/freebsd/sys/contrib/device-tree/Bindings/display/rockchip/ |
H A D | rockchip-lvds.txt | 1 Rockchip RK3288 LVDS interface 5 - compatible: matching the soc type, one of 6 - "rockchip,rk3288-lvds"; 7 - "rockchip,px30-lvds"; 9 - reg: physical base address of the controller and length 11 - clocks: must include clock specifiers corresponding to entries in the 12 clock-names property. 13 - clock-names: must contain "pclk_lvds" 15 - avdd1v0-supply: regulator phandle for 1.0V analog power 16 - avdd1v8-supply: regulator phandle for 1.8V analog power [all …]
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H A D | rockchip,lvds.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,lvds.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Rockchip low-voltage differential signal (LVDS) transmitter 10 - Sandy Huang <hjc@rock-chips.com> 11 - Heiko Stuebner <heiko@sntech.de> 16 - rockchip,px30-lvds 17 - rockchip,rk3288-lvds 25 clock-names: [all …]
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/freebsd/sys/contrib/device-tree/Bindings/display/imx/ |
H A D | ldb.txt | 1 Device-Tree bindings for LVDS Display Bridge (ldb) 3 LVDS Display Bridge 6 The LVDS Display Bridge device tree node contains up to two lvds-channel 7 nodes describing each of the two LVDS encoder channels of the bridge. 10 - #address-cells : should be <1> 11 - #size-cells : should be <0> 12 - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb". 15 interfaces as input for each LVDS channel. 16 - gpr : should be <&gpr> on i.MX53 and i.MX6q. 17 The phandle points to the iomuxc-gpr region containing the LVDS [all …]
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/freebsd/sys/contrib/device-tree/Bindings/display/ |
H A D | amlogic,meson-vpu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Neil Armstrong <neil.armstrong@linaro.org> 17 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------| 19 D |-------| |----| | | | | HDMI PLL | 20 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK | 21 R |-------| |----| Processing | | | | | 22 | osd2 | | | |---| Enci ----------|----|-----VDAC------| [all …]
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H A D | allwinner,sun4i-a10-tcon.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-tcon.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 14 The TCON acts as a timing controller for RGB, LVDS and TV 18 "#clock-cells": 23 - const: allwinner,sun4i-a10-tcon 24 - const: allwinner,sun5i-a13-tcon [all …]
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/freebsd/sys/contrib/device-tree/src/arm/microchip/ |
H A D | at91-nattis-2-natte-2.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * at91-nattis-2-natte-2.dts - Device Tree file for the Linea/Nattis board 9 /dts-v1/; 10 #include "at91-linea.dtsi" 11 #include "at91-natte.dtsi" 14 model = "Axentia Linea-Nattis v2 Natte v2"; 15 compatible = "axentia,nattis-2", "axentia,natte-2", "axentia,linea", 18 gpio-keys { 19 compatible = "gpio-keys"; 21 key-wakeup { [all …]
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/freebsd/sys/contrib/device-tree/Bindings/display/mediatek/ |
H A D | mediatek,dpi.txt | 5 provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel 9 - compatible: "mediatek,<chip>-dpi" 11 - reg: Physical base address and length of the controller's registers 12 - interrupts: The interrupt signal from the function block. 13 - clocks: device clocks 14 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. 15 - clock-names: must contain "pixel", "engine", and "pll" 16 - port: Output port node with endpoint definitions as described in 18 to the input port of an attached HDMI or LVDS encoder chip. 21 - pinctrl-names: Contain "default" and "sleep". [all …]
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H A D | mediatek,dpi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - CK Hu <ck.hu@mediatek.com> 11 - Jitao shi <jitao.shi@mediatek.com> 15 subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a 21 - enum: 22 - mediatek,mt2701-dpi 23 - mediatek,mt7623-dpi 24 - mediatek,mt8173-dpi [all …]
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/freebsd/sys/contrib/device-tree/src/arm/rockchip/ |
H A D | rk3188-bqedison2qc.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 /dts-v1/; 8 #include <dt-bindings/i2c/i2c.h> 9 #include <dt-bindings/input/input.h> 10 #include <dt-bindings/interrupt-controller/irq.h> 14 model = "BQ Edison2 Quad-Core"; 15 compatible = "mundoreader,bq-edison2qc", "rockchip,rk3188"; 29 compatible = "pwm-backlight"; 30 power-supply = <&vsys>; 34 gpio-keys { [all …]
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/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/ |
H A D | imx6dl-b1x5pv2.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT 6 // Copyright 2018-2021 General Electric Company 7 // Copyright 2018-2021 Collabora 9 #include <dt-bindings/input/input.h> 10 #include "imx6dl-qmx6.dtsi" 14 stdout-path = &uart3; 20 operating-points = < 25 fsl,soc-operatin [all...] |
/freebsd/sys/contrib/device-tree/src/arm/renesas/ |
H A D | r8a7779-marzen.dts | 1 // SPDX-License-Identifier: GPL-2.0 3 * Device Tree Source for the R-Car H1 (R8A77790) Marzen board 9 /dts-v1/; 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/input/input.h> 13 #include <dt-bindings/interrupt-controller/irq.h> 26 stdout-pat [all...] |
/freebsd/sys/arm/nvidia/drm2/ |
H A D | tegra_drm.h | 1 /*- 2 * Copyright 1992-2015 Michal Meloun 56 bool flip_x; /* Inverted X-axis */ 57 bool flip_y; /* Inverted Y-axis */ 71 void *panel; /* XXX For LVDS panel */ 77 struct drm_encoder encoder; member
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/freebsd/sys/dev/drm2/ |
H A D | drm_crtc.h | 3 * Copyright © 2007-2008 Dave Airlie 4 * Copyright © 2007-2008 Intel Corporation 62 * control chips as 'CRTCs'. They can control any type of connector, VGA, LVDS, 104 MODE_UNVERIFIED = -3, /* mode needs to reverified */ 105 MODE_BAD = -2, /* unspecified reason */ 106 MODE_ERROR = -1 /* error condition */ 300 * drm_crtc_funcs - control CRTCs for a given device 314 * CRTC is simply historical, a CRTC may control LVDS, VGA, DVI, TV out, etc. 360 * drm_crtc - central CRTC control structure 378 * @helper_private: mid-layer private data [all …]
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H A D | drm_crtc_helper.c | 2 * Copyright (c) 2006-2008 Intel Corporation 41 * drm_helper_move_panel_connectors_to_head() - move panels to the front in the 48 * (eDP/LVDS) panels to the front of the connector list, instead of 59 &dev->mode_config.connector_list, head) { in drm_helper_move_panel_connectors_to_head() 60 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS || in drm_helper_move_panel_connectors_to_head() 61 connector->connector_type == DRM_MODE_CONNECTOR_eDP) in drm_helper_move_panel_connectors_to_head() 62 list_move_tail(&connector->head, &panel_list); in drm_helper_move_panel_connectors_to_head() 65 list_splice(&panel_list, &dev->mode_config.connector_list); in drm_helper_move_panel_connectors_to_head() 80 list_for_each_entry(mode, &connector->modes, head) { in drm_mode_validate_flag() 81 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) && in drm_mode_validate_flag() [all …]
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H A D | drm_crtc.c | 2 * Copyright (c) 2006-2008 Intel Corporation 84 * Non-global properties, but "required" for certain connectors. 88 { DRM_MODE_SUBCONNECTOR_Automatic, "Automatic" }, /* DVI-I and TV-out */ 89 { DRM_MODE_SUBCONNECTOR_DVID, "DVI-D" }, /* DVI-I */ 90 { DRM_MODE_SUBCONNECTOR_DVIA, "DVI-A" }, /* DVI-I */ 97 { DRM_MODE_SUBCONNECTOR_Unknown, "Unknown" }, /* DVI-I and TV-out */ 98 { DRM_MODE_SUBCONNECTOR_DVID, "DVI-D" }, /* DVI-I */ 99 { DRM_MODE_SUBCONNECTOR_DVIA, "DVI-A" }, /* DVI-I */ 107 { DRM_MODE_SUBCONNECTOR_Automatic, "Automatic" }, /* DVI-I and TV-out */ 108 { DRM_MODE_SUBCONNECTOR_Composite, "Composite" }, /* TV-out */ [all …]
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H A D | drm_fb_helper.c | 2 * Copyright (c) 2006-2009 Red Hat Inc. 3 * Copyright (c) 2006-2008 Intel Corporation 62 fb_helper = sc->fb_helper; in vt_restore_fbdev_mode() 63 sx_xlock(&fb_helper->dev->mode_config.mutex); in vt_restore_fbdev_mode() 65 sx_xunlock(&fb_helper->dev->mode_config.mutex); in vt_restore_fbdev_mode() 76 taskqueue_enqueue(taskqueue_thread, &sc->fb_mode_task); in vt_kms_postswitch() 78 drm_fb_helper_restore_fbdev_mode(sc->fb_helper); in vt_kms_postswitch() 92 TASK_INIT(&sc->fb_mode_task, 0, vt_restore_fbdev_mode, sc); in framebuffer_alloc() 94 info->fb_priv = sc; in framebuffer_alloc() 95 info->enter = &vt_kms_postswitch; in framebuffer_alloc() [all …]
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/freebsd/sys/contrib/device-tree/Bindings/display/tegra/ |
H A D | nvidia,tegra124-sor.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-so [all...] |
/freebsd/sys/contrib/device-tree/src/arm64/renesas/ |
H A D | draak.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2016-2018 Renesas Electronics Corp. 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/input/input.h> 21 audio_clkout: audio-clkout { 24 * but needed to avoid cs2000/rcar_sound probe dead-lock 26 compatible = "fixed-clock"; 27 #clock-cell [all...] |
H A D | ebisu.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Device Tree Source for the Ebisu/Ebisu-4D board 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/input/input.h> 33 stdout-path = "serial0:115200n8"; 36 audio_clkout: audio-clkout { 39 * but needed to avoid cs2000/rcar_sound probe dead-lock 41 compatible = "fixed-cloc [all...] |