xref: /freebsd/sys/arm/nvidia/drm2/tegra_drm.h (revision 95ee2897e98f5d444f26ed2334cc7c439f9c16c6)
1a0a23564SMichal Meloun /*-
2a0a23564SMichal Meloun  * Copyright 1992-2015 Michal Meloun
3a0a23564SMichal Meloun  * All rights reserved.
4a0a23564SMichal Meloun  *
5a0a23564SMichal Meloun  * Redistribution and use in source and binary forms, with or without
6a0a23564SMichal Meloun  * modification, are permitted provided that the following conditions
7a0a23564SMichal Meloun  * are met:
8a0a23564SMichal Meloun  * 1. Redistributions of source code must retain the above copyright
9a0a23564SMichal Meloun  *    notice, this list of conditions and the following disclaimer.
10a0a23564SMichal Meloun  * 2. Redistributions in binary form must reproduce the above copyright
11a0a23564SMichal Meloun  *    notice, this list of conditions and the following disclaimer in the
12a0a23564SMichal Meloun  *    documentation and/or other materials provided with the distribution.
13a0a23564SMichal Meloun  *
14a0a23564SMichal Meloun  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15a0a23564SMichal Meloun  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16a0a23564SMichal Meloun  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17a0a23564SMichal Meloun  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18a0a23564SMichal Meloun  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19a0a23564SMichal Meloun  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20a0a23564SMichal Meloun  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21a0a23564SMichal Meloun  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22a0a23564SMichal Meloun  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23a0a23564SMichal Meloun  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24a0a23564SMichal Meloun  * SUCH DAMAGE.
25a0a23564SMichal Meloun  */
26a0a23564SMichal Meloun #ifndef _TEGRA_DRM_H_
27a0a23564SMichal Meloun #define _TEGRA_DRM_H_
28a0a23564SMichal Meloun 
29a0a23564SMichal Meloun #include <dev/gpio/gpiobusvar.h>
30a0a23564SMichal Meloun 
31a0a23564SMichal Meloun struct tegra_bo {
32a0a23564SMichal Meloun  	struct drm_gem_object	gem_obj;
33a0a23564SMichal Meloun 	/* mapped memory buffer */
34a0a23564SMichal Meloun 	vm_paddr_t		pbase;
35a0a23564SMichal Meloun 	vm_offset_t		vbase;
36a0a23564SMichal Meloun 	size_t			npages;
37a0a23564SMichal Meloun 	vm_page_t 		*m;
38a0a23564SMichal Meloun 	vm_object_t		cdev_pager;
39a0a23564SMichal Meloun };
40a0a23564SMichal Meloun 
41a0a23564SMichal Meloun struct tegra_plane {
42a0a23564SMichal Meloun 	struct drm_plane	drm_plane;
43a0a23564SMichal Meloun 	int			index;		/* Window index */
44a0a23564SMichal Meloun };
45a0a23564SMichal Meloun 
46a0a23564SMichal Meloun struct tegra_fb {
47a0a23564SMichal Meloun 	struct drm_framebuffer	drm_fb;
48a0a23564SMichal Meloun 	struct drm_fb_helper	fb_helper;
49a0a23564SMichal Meloun 	struct tegra_bo		**planes;	/* Attached planes */
50a0a23564SMichal Meloun 	int			nplanes;
51a0a23564SMichal Meloun 
52a0a23564SMichal Meloun 	/* Surface and display geometry */
53a0a23564SMichal Meloun 	bool			block_linear;	/* Surface_kind */
54a0a23564SMichal Meloun 	uint32_t		block_height;
55a0a23564SMichal Meloun 	int			rotation; 	/* In degrees */
56a0a23564SMichal Meloun 	bool			flip_x;		/* Inverted X-axis */
57a0a23564SMichal Meloun 	bool			flip_y;		/* Inverted Y-axis */
58a0a23564SMichal Meloun };
59a0a23564SMichal Meloun 
60a0a23564SMichal Meloun struct tegra_crtc {
61a0a23564SMichal Meloun 	struct drm_crtc 	drm_crtc;
62a0a23564SMichal Meloun 	device_t		dev;
63a0a23564SMichal Meloun 	int			nvidia_head;
64a0a23564SMichal Meloun 	vm_paddr_t		cursor_pbase;	/* Cursor buffer */
65*f49fd63aSJohn Baldwin 	void			*cursor_vbase;
66a0a23564SMichal Meloun };
67a0a23564SMichal Meloun 
68a0a23564SMichal Meloun struct tegra_drm_encoder {
69a0a23564SMichal Meloun 	device_t 		dev;
70a0a23564SMichal Meloun 
71a0a23564SMichal Meloun 	void 			*panel;		/* XXX For LVDS panel */
72a0a23564SMichal Meloun 	device_t  		ddc;
73a0a23564SMichal Meloun 	struct edid 		*edid;
74a0a23564SMichal Meloun 
75a0a23564SMichal Meloun 	gpio_pin_t		gpio_hpd;
76a0a23564SMichal Meloun 
77a0a23564SMichal Meloun 	struct drm_encoder 	encoder;
78a0a23564SMichal Meloun 	struct drm_connector 	connector;
79a0a23564SMichal Meloun 	int			(*setup_clock)(struct tegra_drm_encoder *output,
80a0a23564SMichal Meloun 				    clk_t clk, uint64_t pclk);
81a0a23564SMichal Meloun };
82a0a23564SMichal Meloun 
83a0a23564SMichal Meloun struct tegra_drm {
84a0a23564SMichal Meloun 	struct drm_device 	drm_dev;
85a0a23564SMichal Meloun 	struct tegra_fb 	*fb;		/* Prime framebuffer */
86a0a23564SMichal Meloun 	int			pitch_align;
87a0a23564SMichal Meloun };
88a0a23564SMichal Meloun 
89a0a23564SMichal Meloun /* tegra_drm_subr.c */
90a0a23564SMichal Meloun int tegra_drm_encoder_attach(struct tegra_drm_encoder *output, phandle_t node);
91a0a23564SMichal Meloun int tegra_drm_encoder_init(struct tegra_drm_encoder *output,
92a0a23564SMichal Meloun     struct tegra_drm *drm);
93a0a23564SMichal Meloun int tegra_drm_encoder_exit(struct tegra_drm_encoder *output,
94a0a23564SMichal Meloun     struct tegra_drm *drm);
95a0a23564SMichal Meloun enum drm_connector_status tegra_drm_connector_detect(
96a0a23564SMichal Meloun     struct drm_connector *connector, bool force);
97a0a23564SMichal Meloun int tegra_drm_connector_get_modes(struct drm_connector *connector);
98a0a23564SMichal Meloun struct drm_encoder *tegra_drm_connector_best_encoder(
99a0a23564SMichal Meloun     struct drm_connector *connector);
100a0a23564SMichal Meloun 
101a0a23564SMichal Meloun /* tegra_dc.c */
102a0a23564SMichal Meloun void tegra_dc_cancel_page_flip(struct drm_crtc *drm_crtc,
103a0a23564SMichal Meloun     struct drm_file *file);
104a0a23564SMichal Meloun void tegra_dc_enable_vblank(struct drm_crtc *drm_crtc);
105a0a23564SMichal Meloun void tegra_dc_disable_vblank(struct drm_crtc *drm_crtc);
106a0a23564SMichal Meloun int tegra_dc_get_pipe(struct drm_crtc *drm_crtc);
107a0a23564SMichal Meloun 
108a0a23564SMichal Meloun /* tegra_fb.c */
109a0a23564SMichal Meloun struct fb_info *tegra_drm_fb_getinfo(struct drm_device *drm);
110a0a23564SMichal Meloun struct tegra_bo *tegra_fb_get_plane(struct tegra_fb *fb, int idx);
111a0a23564SMichal Meloun int tegra_drm_fb_create(struct drm_device *drm, struct drm_file *file,
112a0a23564SMichal Meloun     struct drm_mode_fb_cmd2 *cmd, struct drm_framebuffer **fb_res);
113a0a23564SMichal Meloun int tegra_drm_fb_init(struct drm_device *drm);
114a0a23564SMichal Meloun void tegra_drm_fb_destroy(struct drm_device *drm);
115a0a23564SMichal Meloun 
116a0a23564SMichal Meloun /* tegra_bo.c */
117a0a23564SMichal Meloun struct tegra_bo;
118a0a23564SMichal Meloun int tegra_bo_create(struct drm_device *drm, size_t size,
119a0a23564SMichal Meloun     struct tegra_bo **res_bo);
120a0a23564SMichal Meloun void tegra_bo_driver_register(struct drm_driver *drm_drv);
121a0a23564SMichal Meloun 
122a0a23564SMichal Meloun #endif /* _TEGRA_DRM_H_ */
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