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/linux/drivers/media/platform/renesas/vsp1/
H A Dvsp1_lut.c28 static inline void vsp1_lut_write(struct vsp1_lut *lut, in vsp1_lut_write() argument
40 static int lut_set_table(struct vsp1_lut *lut, struct v4l2_ctrl *ctrl) in lut_set_table() argument
45 dlb = vsp1_dl_body_get(lut->pool); in lut_set_table()
53 spin_lock_irq(&lut->lock); in lut_set_table()
54 swap(lut->lut, dlb); in lut_set_table()
55 spin_unlock_irq(&lut->lock); in lut_set_table()
63 struct vsp1_lut *lut = in lut_s_ctrl() local
68 lut_set_table(lut, ctrl); in lut_s_ctrl()
154 struct vsp1_lut *lut = to_lut(&entity->subdev); in lut_configure_stream() local
156 vsp1_lut_write(lut, dlb, VI6_LUT_CTRL, VI6_LUT_CTRL_EN); in lut_configure_stream()
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/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_util.h98 * @ lut_flag: scaler LUT update flags
99 * 0x1 swap LUT bank
100 * 0x2 update 2D filter LUT
101 * 0x4 update y circular filter LUT
102 * 0x8 update uv circular filter LUT
103 * 0x10 update y separable filter LUT
104 * 0x20 update uv separable filter LUT
105 * @ dir_lut_idx: 2D filter LUT index
106 * @ y_rgb_cir_lut_idx: y circular filter LUT index
107 * @ uv_cir_lut_idx: uv circular filter LUT index
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H A Ddpu_hw_util.c119 u32 *lut[QSEED3_FILTERS] = {NULL, NULL, NULL, NULL, NULL}; in _dpu_hw_setup_scaler3_lut() local
131 lut[0] = scaler3_cfg->dir_lut; in _dpu_hw_setup_scaler3_lut()
137 lut[1] = scaler3_cfg->cir_lut + in _dpu_hw_setup_scaler3_lut()
144 lut[2] = scaler3_cfg->cir_lut + in _dpu_hw_setup_scaler3_lut()
151 lut[3] = scaler3_cfg->sep_lut + in _dpu_hw_setup_scaler3_lut()
158 lut[4] = scaler3_cfg->sep_lut + in _dpu_hw_setup_scaler3_lut()
165 if (!lut[filter]) in _dpu_hw_setup_scaler3_lut()
175 (lut[filter])[lut_offset++]); in _dpu_hw_setup_scaler3_lut()
194 u32 *lut[QSEED3LITE_FILTERS] = {NULL, NULL}; in _dpu_hw_setup_scaler3lite_lut() local
206 lut[0] = scaler3_cfg->sep_lut + in _dpu_hw_setup_scaler3lite_lut()
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/linux/drivers/video/fbdev/
H A Dmacfb.c58 unsigned char lut; member
64 unsigned char lut; member
73 unsigned char lut; member
79 unsigned char lut; /* OFFSET: 0x10 */ member
101 unsigned char lut; member
106 unsigned char lut; /* TFBClutWDataReg, offset 0x90018 */ member
114 unsigned char lut; member
167 &dafb_cmap_regs->lut); in dafb_setpalette()
170 &dafb_cmap_regs->lut); in dafb_setpalette()
173 &dafb_cmap_regs->lut); in dafb_setpalette()
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/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Dlut.c22 #include "lut.h"
32 nv50_lut_load(struct nv50_lut *lut, int buffer, struct drm_property_blob *blob, in nv50_lut_load() argument
36 void __iomem *mem = lut->mem[buffer].object.map.ptr; in nv50_lut_load()
37 const u32 addr = lut->mem[buffer].addr; in nv50_lut_load()
59 nv50_lut_fini(struct nv50_lut *lut) in nv50_lut_fini() argument
62 for (i = 0; i < ARRAY_SIZE(lut->mem); i++) in nv50_lut_fini()
63 nvif_mem_dtor(&lut->mem[i]); in nv50_lut_fini()
68 struct nv50_lut *lut) in nv50_lut_init() argument
72 for (i = 0; i < ARRAY_SIZE(lut->mem); i++) { in nv50_lut_init()
74 size * 8, &lut->mem[i]); in nv50_lut_init()
/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_cmm.h19 * @lut: 1D-LUT configuration
20 * @lut.table: 1D-LUT table entries. Disable LUT operations when NULL
25 } lut; member
/linux/drivers/gpio/
H A Dgpio-adp5520.c19 unsigned char lut[ADP5520_MAXGPIOS]; member
40 return !!(reg_val & dev->lut[off]); in adp5520_gpio_get_value()
51 dev->lut[off]); in adp5520_gpio_set_value()
54 dev->lut[off]); in adp5520_gpio_set_value()
65 dev->lut[off]); in adp5520_gpio_direction_input()
79 dev->lut[off]); in adp5520_gpio_direction_output()
82 dev->lut[off]); in adp5520_gpio_direction_output()
85 dev->lut[off]); in adp5520_gpio_direction_output()
116 dev->lut[gpios++] = 1 << i; in adp5520_gpio_probe()
/linux/drivers/net/ethernet/aquantia/atlantic/macsec/
H A DMSS_Ingress_registers.h50 * (IGPRCTLF) LUT
51 * 0x1 : Ingress Pre-Security Classification LUT (IGPRC)
52 * 0x2 : Ingress Packet Format (IGPFMT) SAKey LUT
53 * 0x3 : Ingress Packet Format (IGPFMT) SC/SA LUT
54 * 0x4 : Ingress Post-Security Classification LUT
57 * (IGPOCTLF) LUT
H A DMSS_Egress_registers.h51 /* 0x0 : Egress MAC Control FIlter (CTLF) LUT
52 * 0x1 : Egress Classification LUT
53 * 0x2 : Egress SC/SA LUT
/linux/drivers/clk/rockchip/
H A Dsoftrst.c15 const int *lut; member
31 if (softrst->lut) in rockchip_softrst_assert()
32 id = softrst->lut[id]; in rockchip_softrst_assert()
63 if (softrst->lut) in rockchip_softrst_deassert()
64 id = softrst->lut[id]; in rockchip_softrst_deassert()
106 softrst->lut = lookup_table; in rockchip_register_softrst_lut()
/linux/drivers/gpu/drm/mediatek/
H A Dmtk_disp_aal.c82 * mtk_aal_gamma_get_lut_size() - Get gamma LUT size for AAL
85 * Return: 0 if gamma control not supported in AAL or gamma LUT size
99 struct drm_color_lut *lut; in mtk_aal_gamma_set() local
107 /* Also, if there's no gamma lut there's nothing to do here. */ in mtk_aal_gamma_set()
111 lut = (struct drm_color_lut *)state->gamma_lut->data; in mtk_aal_gamma_set()
114 .red = drm_color_lut_extract(lut[i].red, DISP_AAL_LUT_BITS), in mtk_aal_gamma_set()
115 .green = drm_color_lut_extract(lut[i].green, DISP_AAL_LUT_BITS), in mtk_aal_gamma_set()
116 .blue = drm_color_lut_extract(lut[i].blue, DISP_AAL_LUT_BITS) in mtk_aal_gamma_set()
/linux/drivers/net/ethernet/intel/iavf/
H A Diavf_common.c259 * @lut: pointer to the lut buffer provided by the caller
260 * @lut_size: size of the lut buffer
267 u8 *lut, u16 lut_size, in iavf_aq_get_set_rss_lut() argument
301 status = iavf_asq_send_command(hw, &desc, lut, lut_size, NULL); in iavf_aq_get_set_rss_lut()
311 * @lut: pointer to the lut buffer provided by the caller
312 * @lut_size: size of the lut buffer
317 bool pf_lut, u8 *lut, u16 lut_size) in iavf_aq_set_rss_lut() argument
319 return iavf_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true); in iavf_aq_set_rss_lut()
/linux/drivers/gpu/drm/arm/
H A Dmalidp_crtc.c130 struct drm_color_lut *lut = (struct drm_color_lut *)lut_blob->data; in malidp_generate_gamma_table() local
138 out_start = drm_color_lut_extract(lut[segments[i].start].green, in malidp_generate_gamma_table()
140 out_end = drm_color_lut_extract(lut[segments[i].end].green, 12); in malidp_generate_gamma_table()
148 * Check if there is a new gamma LUT and if it is of an acceptable size. Also,
155 struct drm_color_lut *lut; in malidp_crtc_atomic_check_gamma() local
173 lut = (struct drm_color_lut *)state->gamma_lut->data; in malidp_crtc_atomic_check_gamma()
175 if (!((lut[i].red == lut[i].green) && in malidp_crtc_atomic_check_gamma()
176 (lut[i].red == lut[i].blue))) in malidp_crtc_atomic_check_gamma()
186 * changing the gamma LUT doesn't depend on any external in malidp_crtc_atomic_check_gamma()
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
H A Ddcn30_dpp.c66 // Shaper LUT (RAM), 3D LUT (mode, bit-depth, size) in dpp30_read_state()
535 ASSERT(0); // LUT select was updated again before vupdate in dpp3_deferred_update()
544 ASSERT(0); // LUT select was updated again before vupdate in dpp3_deferred_update()
553 ASSERT(0); // LUT select was updated again before vupdate in dpp3_deferred_update()
562 ASSERT(0); // LUT select was updated again before vupdate in dpp3_deferred_update()
697 /*program blnd lut RAM A*/
725 /*program blnd lut RAM B*/
1321 const struct dc_rgb *lut, in dpp3_set3dlut_ram12() argument
1328 red = lut[i].red<<4; in dpp3_set3dlut_ram12()
1329 green = lut[i].green<<4; in dpp3_set3dlut_ram12()
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/linux/drivers/hwmon/
H A Dmax31760.c47 } lut[LUT_SIZE]; member
491 struct lut_attribute *lut; in max31760_create_lut_nodes() local
494 lut = &state->lut[i]; in max31760_create_lut_nodes()
495 sda = &lut->sda; in max31760_create_lut_nodes()
497 snprintf(lut->name, sizeof(lut->name), in max31760_create_lut_nodes()
504 sda->dev_attr.attr.name = lut->name; in max31760_create_lut_nodes()
/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sm6115-dpu.yaml33 - description: Display lut
42 - const: lut
73 clock-names = "bus", "iface", "core", "lut", "rot", "vsync";
H A Dqcom,qcm2290-dpu.yaml33 - description: Display lut clock from dispcc
41 - const: lut
70 clock-names = "bus", "iface", "core", "lut", "vsync";
H A Dqcom,sc7180-dpu.yaml38 - description: Display lut clock
49 - const: lut
98 clock-names = "bus", "iface", "rot", "lut", "core",
H A Dqcom,sm7150-dpu.yaml33 - description: Display lut clock
42 - const: lut
75 "lut",
/linux/Documentation/hwmon/
H A Dmax31760.rst28 reading as an index to a 48-byte lookup table (LUT) containing
29 user-programmed PWM values. The flexible LUT-based architecture enables
47 LUT Index Name
75 pwm1_auto_point[1-48]_pwm PWM value for LUT point
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_ipp.c163 /* If prescale is in use, then legacy lut should be bypassed */ in dce_ipp_program_prescale()
176 /* power on LUT memory */ in dce_ipp_program_input_lut()
186 /* LUT-256, unsigned, integer, new u0.12 format */ in dce_ipp_program_input_lut()
208 /* power off LUT memory */ in dce_ipp_program_input_lut()
212 /* bypass prescale, enable legacy LUT */ in dce_ipp_program_input_lut()
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/
H A Ddcn20_dpp_cm.c440 /*program blnd lut RAM A*/
468 /*program blnd lut RAM B*/
1051 const struct dc_rgb *lut, in dpp20_set3dlut_ram12() argument
1058 red = lut[i].red<<4; in dpp20_set3dlut_ram12()
1059 green = lut[i].green<<4; in dpp20_set3dlut_ram12()
1060 blue = lut[i].blue<<4; in dpp20_set3dlut_ram12()
1061 red1 = lut[i+1].red<<4; in dpp20_set3dlut_ram12()
1062 green1 = lut[i+1].green<<4; in dpp20_set3dlut_ram12()
1063 blue1 = lut[i+1].blue<<4; in dpp20_set3dlut_ram12()
1081 * load selected lut with 10 bits color channels
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/linux/drivers/net/wireless/ti/wl1251/
H A Dboot.c70 static const u32 LUT[REF_FREQ_NUM][LUT_PARAM_NUM] = { in wl1251_boot_init_seq() local
143 tmp = LUT[ref_freq][LUT_PARAM_INTEGER_DIVIDER] | 0x00017000; in wl1251_boot_init_seq()
149 tmp = LUT[ref_freq][LUT_PARAM_FRACTIONAL_DIVIDER]; in wl1251_boot_init_seq()
160 tmp = (LUT[ref_freq][LUT_PARAM_ATTN_BB] << 16) | in wl1251_boot_init_seq()
161 (LUT[ref_freq][LUT_PARAM_ALPHA_BB] << 12) | 0x1; in wl1251_boot_init_seq()
168 tmp = LUT[ref_freq][LUT_PARAM_STOP_TIME_BB] | 0x000A0000; in wl1251_boot_init_seq()
176 tmp = LUT[ref_freq][LUT_PARAM_BB_PLL_LOOP_FILTER] | 0x00000030; in wl1251_boot_init_seq()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc.h170 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs,
173 * @dgam_ram: programmable degamma LUT
176 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared
178 * @ogam_ram: programmable out/blend gamma LUT
180 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes
181 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT
182 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
204 uint32_t dma_3d_lut : 1; /*< DMA mode support for 3D LUT */
221 uint32_t dim_9 : 1; /* 3D LUT support for 9x9x9 */
222 uint32_t dim_17 : 1; /* 3D LUT support for 17x17x17 */
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/linux/drivers/clk/tegra/
H A Dclk-dfll.c186 /* MAX_DFLL_VOLTAGES: number of LUT entries in the DFLL IP block */
248 * @lut_index: LUT index at which voltage the dvco_target_rate will be reached
302 /* lut array entries are regulator framework selectors or PWM values*/
303 unsigned lut[MAX_DFLL_VOLTAGES]; member
690 td->lut[lut_index]); in dfll_load_i2c_lut()
787 * find_lut_index_for_rate - determine I2C LUT index for given DFLL rate
791 * Determines the index of a I2C LUT entry for a voltage that approximately
794 * LUT index is not found.
1660 td->lut[i] = i; in dfll_build_pwm_lut()
1698 * On success, fills in td->lut and returns 0, or -err on failure.
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