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/linux/include/drm/
H A Ddrm_color_mgmt.h34 * drm_color_lut_extract - clamp and round LUT entries
36 * @bit_precision: number of bits the hw LUT supports
38 * Extract a degamma/gamma LUT value provided by user (in the form of
54 * drm_color_lut32_extract - clamp and round LUT entries
56 * @bit_precision: number of bits the hw LUT supports
58 * Extract U0.bit_precision from a U0.32 LUT value.
80 * drm_color_lut_size - calculate the number of entries in the LUT
81 * @blob: blob containing the LUT
84 * The number of entries in the color LUT stored in @blob.
92 * drm_color_lut32_size - calculate the number of entries in the extended LUT
[all …]
/linux/drivers/net/wireless/ath/ath11k/
H A Dcfr.c54 void ath11k_cfr_release_lut_entry(struct ath11k_look_up_table *lut) in ath11k_cfr_release_lut_entry() argument
56 memset(lut, 0, sizeof(*lut)); in ath11k_cfr_release_lut_entry()
77 struct ath11k_look_up_table *lut; in ath11k_cfr_free_pending_dbr_events() local
80 if (!cfr->lut) in ath11k_cfr_free_pending_dbr_events()
84 lut = &cfr->lut[i]; in ath11k_cfr_free_pending_dbr_events()
85 if (lut->dbr_recv && !lut->tx_recv && in ath11k_cfr_free_pending_dbr_events()
86 lut->dbr_tstamp < cfr->last_success_tstamp) { in ath11k_cfr_free_pending_dbr_events()
87 ath11k_dbring_bufs_replenish(ar, &cfr->rx_ring, lut->buff, in ath11k_cfr_free_pending_dbr_events()
89 ath11k_cfr_release_lut_entry(lut); in ath11k_cfr_free_pending_dbr_events()
98 * @lut: Lookup table for correlation
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/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Dlut.c22 #include "lut.h"
32 nv50_lut_load(struct nv50_lut *lut, int buffer, struct drm_property_blob *blob, in nv50_lut_load() argument
36 void __iomem *mem = lut->mem[buffer].object.map.ptr; in nv50_lut_load()
37 const u32 addr = lut->mem[buffer].addr; in nv50_lut_load()
59 nv50_lut_fini(struct nv50_lut *lut) in nv50_lut_fini() argument
62 for (i = 0; i < ARRAY_SIZE(lut->mem); i++) in nv50_lut_fini()
63 nvif_mem_dtor(&lut->mem[i]); in nv50_lut_fini()
68 struct nv50_lut *lut) in nv50_lut_init() argument
72 for (i = 0; i < ARRAY_SIZE(lut->mem); i++) { in nv50_lut_init()
74 size * 8, &lut->mem[i]); in nv50_lut_init()
/linux/drivers/gpio/
H A Dgpio-adp5520.c19 unsigned char lut[ADP5520_MAXGPIOS]; member
40 return !!(reg_val & dev->lut[off]); in adp5520_gpio_get_value()
51 dev->lut[off]); in adp5520_gpio_set_value()
54 dev->lut[off]); in adp5520_gpio_set_value()
65 dev->lut[off]); in adp5520_gpio_direction_input()
79 dev->lut[off]); in adp5520_gpio_direction_output()
82 dev->lut[off]); in adp5520_gpio_direction_output()
85 dev->lut[off]); in adp5520_gpio_direction_output()
116 dev->lut[gpios++] = 1 << i; in adp5520_gpio_probe()
/linux/drivers/net/ethernet/aquantia/atlantic/macsec/
H A DMSS_Ingress_registers.h50 * (IGPRCTLF) LUT
51 * 0x1 : Ingress Pre-Security Classification LUT (IGPRC)
52 * 0x2 : Ingress Packet Format (IGPFMT) SAKey LUT
53 * 0x3 : Ingress Packet Format (IGPFMT) SC/SA LUT
54 * 0x4 : Ingress Post-Security Classification LUT
57 * (IGPOCTLF) LUT
H A DMSS_Egress_registers.h51 /* 0x0 : Egress MAC Control FIlter (CTLF) LUT
52 * 0x1 : Egress Classification LUT
53 * 0x2 : Egress SC/SA LUT
/linux/drivers/clk/rockchip/
H A Dsoftrst.c15 const int *lut; member
31 if (softrst->lut) in rockchip_softrst_assert()
32 id = softrst->lut[id]; in rockchip_softrst_assert()
63 if (softrst->lut) in rockchip_softrst_deassert()
64 id = softrst->lut[id]; in rockchip_softrst_deassert()
106 softrst->lut = lookup_table; in rockchip_register_softrst_lut()
/linux/Documentation/gpu/rfc/
H A Dcolor_pipeline.rst126 * custom (uniform) 1D LUT
129 * 3D LUT
147 …├─ "TYPE": immutable enum {1D enumerated curve, 1D LUT, 3x3 matrix, 3x4 matrix, 3D LUT, etc.} = 1D…
152 /* custom 4k entry 1D LUT */
154 …├─ "TYPE": immutable enum {1D enumerated curve, 1D LUT, 3x3 matrix, 3x4 matrix, 3D LUT, etc.} = 1D…
160 /* 17^3 3D LUT */
162 …├─ "TYPE": immutable enum {1D enumerated curve, 1D LUT, 3x3 matrix, 3x4 matrix, 3D LUT, etc.} = 3D…
266 ├─ "TYPE" (immutable) = 1D LUT
272 ├─ "TYPE" (immutable) = 3D LUT
/linux/drivers/gpu/drm/mediatek/
H A Dmtk_disp_aal.c82 * mtk_aal_gamma_get_lut_size() - Get gamma LUT size for AAL
85 * Return: 0 if gamma control not supported in AAL or gamma LUT size
99 struct drm_color_lut *lut; in mtk_aal_gamma_set() local
107 /* Also, if there's no gamma lut there's nothing to do here. */ in mtk_aal_gamma_set()
111 lut = (struct drm_color_lut *)state->gamma_lut->data; in mtk_aal_gamma_set()
114 .red = drm_color_lut_extract(lut[i].red, DISP_AAL_LUT_BITS), in mtk_aal_gamma_set()
115 .green = drm_color_lut_extract(lut[i].green, DISP_AAL_LUT_BITS), in mtk_aal_gamma_set()
116 .blue = drm_color_lut_extract(lut[i].blue, DISP_AAL_LUT_BITS) in mtk_aal_gamma_set()
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_dspp.h41 * struct dpu_hw_gc_lut - gc lut feature structure
44 * @c0: color0 component lut
45 * @c1: color1 component lut
46 * @c2: color2 component lut
71 * @gc_lut: Pointer to lut content
/linux/drivers/net/ethernet/intel/iavf/
H A Diavf_common.c259 * @lut: pointer to the lut buffer provided by the caller
260 * @lut_size: size of the lut buffer
267 u8 *lut, u16 lut_size, in iavf_aq_get_set_rss_lut() argument
301 status = iavf_asq_send_command(hw, &desc, lut, lut_size, NULL); in iavf_aq_get_set_rss_lut()
311 * @lut: pointer to the lut buffer provided by the caller
312 * @lut_size: size of the lut buffer
317 bool pf_lut, u8 *lut, u16 lut_size) in iavf_aq_set_rss_lut() argument
319 return iavf_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true); in iavf_aq_set_rss_lut()
/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sm6115-dpu.yaml33 - description: Display lut
42 - const: lut
73 clock-names = "bus", "iface", "core", "lut", "rot", "vsync";
H A Dqcom,sc7180-dpu.yaml38 - description: Display lut clock
49 - const: lut
98 clock-names = "bus", "iface", "rot", "lut", "core",
H A Dqcom,sm7150-dpu.yaml33 - description: Display lut clock
42 - const: lut
75 "lut",
/linux/Documentation/hwmon/
H A Dmax31760.rst28 reading as an index to a 48-byte lookup table (LUT) containing
29 user-programmed PWM values. The flexible LUT-based architecture enables
47 LUT Index Name
75 pwm1_auto_point[1-48]_pwm PWM value for LUT point
/linux/drivers/gpu/drm/sysfb/
H A Dvesadrm.c94 * Color LUT
180 struct drm_color_lut *lut) in vesadrm_load_gamma_lut() argument
187 drm_crtc_load_gamma_555_from_888(crtc, lut, vesadrm_set_color_lut); in vesadrm_load_gamma_lut()
190 drm_crtc_load_gamma_565_from_888(crtc, lut, vesadrm_set_color_lut); in vesadrm_load_gamma_lut()
195 drm_crtc_load_gamma_888(crtc, lut, vesadrm_set_color_lut); in vesadrm_load_gamma_lut()
226 struct drm_color_lut *lut) in vesadrm_load_palette_lut() argument
233 drm_crtc_load_palette_8(crtc, lut, vesadrm_set_color_lut); in vesadrm_load_palette_lut()
329 * The gamma LUT has to be reloaded after changing the primary in vesadrm_crtc_helper_atomic_flush()
/linux/drivers/gpu/drm/vkms/
H A Dvkms_composer.h22 s64 get_lut_index(const struct vkms_color_lut *lut, u16 channel_value);
23 u16 apply_lut_to_channel_value(const struct vkms_color_lut *lut, u16 channel_value,
/linux/drivers/net/wireless/ti/wl1251/
H A Dboot.c70 static const u32 LUT[REF_FREQ_NUM][LUT_PARAM_NUM] = { in wl1251_boot_init_seq() local
143 tmp = LUT[ref_freq][LUT_PARAM_INTEGER_DIVIDER] | 0x00017000; in wl1251_boot_init_seq()
149 tmp = LUT[ref_freq][LUT_PARAM_FRACTIONAL_DIVIDER]; in wl1251_boot_init_seq()
160 tmp = (LUT[ref_freq][LUT_PARAM_ATTN_BB] << 16) | in wl1251_boot_init_seq()
161 (LUT[ref_freq][LUT_PARAM_ALPHA_BB] << 12) | 0x1; in wl1251_boot_init_seq()
168 tmp = LUT[ref_freq][LUT_PARAM_STOP_TIME_BB] | 0x000A0000; in wl1251_boot_init_seq()
176 tmp = LUT[ref_freq][LUT_PARAM_BB_PLL_LOOP_FILTER] | 0x00000030; in wl1251_boot_init_seq()
/linux/drivers/clk/tegra/
H A Dclk-dfll.c186 /* MAX_DFLL_VOLTAGES: number of LUT entries in the DFLL IP block */
248 * @lut_index: LUT index at which voltage the dvco_target_rate will be reached
302 /* lut array entries are regulator framework selectors or PWM values*/
303 unsigned lut[MAX_DFLL_VOLTAGES]; member
690 td->lut[lut_index]); in dfll_load_i2c_lut()
787 * find_lut_index_for_rate - determine I2C LUT index for given DFLL rate
791 * Determines the index of a I2C LUT entry for a voltage that approximately
794 * LUT index is not found.
1660 td->lut[i] = i; in dfll_build_pwm_lut()
1698 * On success, fills in td->lut and returns 0, or -err on failure.
[all …]
/linux/drivers/spi/
H A Dspi-nxp-fspi.c14 * FlexSPI controller is driven by the LUT(Look-up Table) registers
15 * LUT registers are a look-up-table for sequences of instructions.
16 * A valid sequence consists of four LUT registers.
17 * Maximum 32 LUT sequences can be programmed simultaneously.
20 * from the spi-mem framework, thus using single LUT index.
267 /* Instruction set for the LUT register. */
298 * Calculate number of required PAD bits for LUT register.
308 * Macro for constructing the LUT entries with the following
319 /* Macros for constructing the LUT register. */
682 /* unlock LUT */ in nxp_fspi_prepare_lut()
[all …]
/linux/drivers/net/wireless/ath/ath12k/
H A Ddp.c1413 struct ath12k_reo_q_addr_lut *lut) in ath12k_dp_alloc_reoq_lut() argument
1415 lut->size = DP_REOQ_LUT_SIZE + HAL_REO_QLUT_ADDR_ALIGN - 1; in ath12k_dp_alloc_reoq_lut()
1416 lut->vaddr_unaligned = dma_alloc_coherent(ab->dev, lut->size, in ath12k_dp_alloc_reoq_lut()
1417 &lut->paddr_unaligned, in ath12k_dp_alloc_reoq_lut()
1419 if (!lut->vaddr_unaligned) in ath12k_dp_alloc_reoq_lut()
1422 lut->vaddr = PTR_ALIGN(lut->vaddr_unaligned, HAL_REO_QLUT_ADDR_ALIGN); in ath12k_dp_alloc_reoq_lut()
1423 lut->paddr = lut->paddr_unaligned + in ath12k_dp_alloc_reoq_lut()
1424 ((unsigned long)lut->vaddr - (unsigned long)lut->vaddr_unaligned); in ath12k_dp_alloc_reoq_lut()
1452 /* Bits in the register have address [39:8] LUT base address to be in ath12k_dp_reoq_lut_setup()
/linux/arch/arm/boot/dts/amlogic/
H A Dmeson8m2.dtsi19 /delete-node/ video-lut@20;
21 canvas: video-lut@48 {
/linux/drivers/tty/vt/
H A Dselection.c115 * sel_loadlut() - load the LUT table
116 * @lut: user table
118 * Load the LUT table from user space. Make a temporary copy so a partial
123 int sel_loadlut(u32 __user *lut) in sel_loadlut() argument
127 if (copy_from_user(tmplut, lut, sizeof(inwordLut))) in sel_loadlut()
/linux/drivers/net/ethernet/google/gve/
H A Dgve_adminq.c1013 "RSS device option enabled with key size of %u, lut size of %u.\n", in gve_enable_supported_features()
1337 __be32 *lut = NULL; in gve_adminq_configure_rss() local
1363 lut = dma_alloc_coherent(&priv->pdev->dev, in gve_adminq_configure_rss()
1364 priv->rss_lut_size * sizeof(*lut), in gve_adminq_configure_rss()
1366 if (!lut) in gve_adminq_configure_rss()
1370 lut[i] = cpu_to_be32(hash_lut_to_config[i]); in gve_adminq_configure_rss()
1418 if (lut) in gve_adminq_configure_rss()
1420 priv->rss_lut_size * sizeof(*lut), in gve_adminq_configure_rss()
1421 lut, lut_bus); in gve_adminq_configure_rss()
1513 __be32 *lut; in gve_adminq_process_rss_query() local
[all …]
/linux/drivers/gpu/drm/omapdrm/
H A Domap_dmm_priv.h114 * This is used in programming to address the upper portion of the LUT
178 /* array of LUT - TCM containers */

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