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Searched +full:ls1b +full:- +full:clk (Results 1 – 6 of 6) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Dloongson,ls1x-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/loongson,ls1x-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-1 Clock Controller
10 - Keguang Zhang <keguang.zhang@gmail.com>
15 - loongson,ls1b-clk
16 - loongson,ls1c-clk
24 "#clock-cells":
28 - compatible
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/linux/Documentation/devicetree/bindings/net/
H A Dloongson,ls1b-gmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/loongson,ls1b-gmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-1B Gigabit Ethernet MAC Controller
10 - Keguang Zhang <keguang.zhang@gmail.com>
13 Loongson-1B Gigabit Ethernet MAC Controller is based on
17 - Dual 10/100/1000Mbps GMAC controllers
18 - Full-duplex operation (IEEE 802.3x flow control automatic transmission)
19 - Half-duplex operation (CSMA/CD Protocol and back-pressure support)
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/linux/Documentation/devicetree/bindings/watchdog/
H A Dloongson,ls1x-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/loongson,ls1x-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-1 Watchdog Timer
10 - Keguang Zhang <keguang.zhang@gmail.com>
13 - $ref: watchdog.yaml#
18 - loongson,ls1b-wdt
19 - loongson,ls1c-wdt
28 - compatible
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/linux/Documentation/devicetree/bindings/timer/
H A Dloongson,ls1x-pwmtimer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/loongson,ls1x-pwmtimer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-1 PWM timer
10 - Keguang Zhang <keguang.zhang@gmail.com>
13 Loongson-1 PWM timer can be used for system clock source
18 const: loongson,ls1b-pwmtimer
30 - compatible
31 - reg
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/linux/drivers/watchdog/
H A Dloongson1_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk.h>
28 struct clk *clk; member
37 writel(0x1, drvdata->base + WDT_SET); in ls1x_wdt_ping()
46 unsigned int max_hw_heartbeat = wdt_dev->max_hw_heartbeat_ms / 1000; in ls1x_wdt_set_timeout()
49 wdt_dev->timeout = timeout; in ls1x_wdt_set_timeout()
51 counts = drvdata->clk_rate * min(timeout, max_hw_heartbeat); in ls1x_wdt_set_timeout()
52 writel(counts, drvdata->base + WDT_TIMER); in ls1x_wdt_set_timeout()
61 writel(0x1, drvdata->base + WDT_EN); in ls1x_wdt_start()
70 writel(0x0, drvdata->base + WDT_EN); in ls1x_wdt_stop()
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/linux/drivers/clk/
H A Dclk-loongson1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Clock driver for Loongson-1 SoC
5 * Copyright (C) 2012-2023 Keguang Zhang <keguang.zhang@gmail.com>
9 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/loongson,ls1x-clk.h>
64 const struct ls1x_clk_pll_data *d = ls1x_clk->data; in ls1x_pll_recalc_rate()
67 val = readl(ls1x_clk->reg); in ls1x_pll_recalc_rate()
68 rate = d->fixed; in ls1x_pll_recalc_rate()
69 rate += ls1x_pll_rate_part(val, d->int_shift, d->int_width); in ls1x_pll_recalc_rate()
70 if (d->frac_width) in ls1x_pll_recalc_rate()
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