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Searched +full:ls1021a +full:- +full:scfg (Results 1 – 13 of 13) sorted by relevance

/linux/Documentation/devicetree/bindings/soc/fsl/
H A Dfsl,layerscape-scfg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/fsl,layerscape-scfg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
13 SCFG is the supplemental configuration unit, that provides SoC specific
20 - enum:
21 - fsl,ls1012a-scfg
22 - fsl,ls1021a-scfg
23 - fsl,ls1028a-scfg
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/linux/arch/arm/boot/dts/nxp/ls/
H A Dls1021a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
12 interrupt-parent = <&gic>;
30 #address-cells = <1>;
31 #size-cells = <0>;
34 compatible = "arm,cortex-a7";
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/linux/drivers/gpu/drm/fsl-dcu/
H A Dfsl_dcu_drm_drv.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
56 struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; in fsl_dcu_irq_reset()
58 regmap_write(fsl_dev->regmap, DCU_INT_STATUS, ~0); in fsl_dcu_irq_reset()
59 regmap_write(fsl_dev->regmap, DCU_INT_MASK, ~0); in fsl_dcu_irq_reset()
65 struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; in fsl_dcu_drm_irq()
69 ret = regmap_read(fsl_dev->regmap, DCU_INT_STATUS, &int_status); in fsl_dcu_drm_irq()
71 dev_err(dev->dev, "read DCU_INT_STATUS failed\n"); in fsl_dcu_drm_irq()
78 regmap_write(fsl_dev->regmap, DCU_INT_STATUS, int_status); in fsl_dcu_drm_irq()
86 return -ENOTCONN; in fsl_dcu_irq_install()
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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1043a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
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H A Dfsl-ls1012a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1012A family SoC.
6 * Copyright 2019-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
23 rtic-a = &rtic_a;
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H A Dfsl-ls1046a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1046A family SoC.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
37 #address-cells = <1>;
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H A Dfsl-ls1028a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
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/linux/drivers/pci/controller/dwc/
H A Dpci-layerscape.c1 // SPDX-License-Identifier: GPL-2.0
26 #include "pcie-designware.h"
31 #define PCIE_ABSERR_SETTING 0x9401 /* Forward error of non-posted request */
38 /* LS1021A PEXn PM Write Control Register */
46 #define PEXPME(idx) BIT(31 - (idx) * 4)
67 struct regmap *scfg; member
73 #define to_ls_pcie(x) dev_get_drvdata((x)->dev)
77 struct dw_pcie *pci = pcie->pci; in ls_pcie_is_bridge()
80 header_type = ioread8(pci->dbi_base + PCI_HEADER_TYPE); in ls_pcie_is_bridge()
86 /* Clear multi-function bit */
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dfsl,ls-extirq.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-extirq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
13 Some Layerscape SOCs (LS1021A, LS1043A, LS1046A LS1088A, LS208xA,
20 - enum:
21 - fsl,ls1021a-extirq
22 - fsl,ls1043a-extirq
23 - fsl,ls1088a-extirq
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H A Dfsl,ls-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Layerscape SCFG PCIe MSI controller
11 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
12 platforms. If interrupt-parent is not provided, the default parent interrupt
15 Each PCIe node needs to have property msi-parent that points to
19 - Frank Li <Frank.Li@nxp.com>
24 - fsl,ls1012a-msi
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/linux/Documentation/devicetree/bindings/pci/
H A Dfsl,layerscape-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
16 which is used to describe the PLL settings at the time of chip-reset.
26 - enum:
27 - fsl,ls1012a-pcie
28 - fsl,ls1021a-pcie
29 - fsl,ls1028a-pcie
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/linux/drivers/irqchip/
H A Dirq-ls-extirq.c1 // SPDX-License-Identifier: GPL-2.0
3 #define pr_fmt(fmt) "irq-ls-extirq: " fmt
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
33 * IRQ descriptors, making sure the read-modify-write is atomic. in ls_extirq_intpcr_rmw()
35 raw_spin_lock(&priv->lock); in ls_extirq_intpcr_rmw()
37 if (priv->big_endian) in ls_extirq_intpcr_rmw()
38 intpcr = ioread32be(priv->intpcr); in ls_extirq_intpcr_rmw()
40 intpcr = ioread32(priv->intpcr); in ls_extirq_intpcr_rmw()
45 if (priv->big_endian) in ls_extirq_intpcr_rmw()
46 iowrite32be(intpcr, priv->intpcr); in ls_extirq_intpcr_rmw()
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H A Dirq-ls-scfg-msi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Freescale SCFG MSI(-X) support
77 if (p && strncmp(p, "no-affinity", 11) == 0) in early_parse_ls_scfg_msi()
90 msg->address_hi = upper_32_bits(msi_data->msiir_addr); in ls_scfg_msi_compose_msg()
91 msg->address_lo = lower_32_bits(msi_data->msiir_addr); in ls_scfg_msi_compose_msg()
92 msg->data = data->hwirq; in ls_scfg_msi_compose_msg()
98 msg->data |= cpumask_first(mask); in ls_scfg_msi_compose_msg()
111 return -EINVAL; in ls_scfg_msi_set_affinity()
118 if (cpu >= msi_data->msir_num) in ls_scfg_msi_set_affinity()
119 return -EINVAL; in ls_scfg_msi_set_affinity()
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