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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ddr/
H A Dlpddr3.txt1 * LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C
4 - compatible : Should be "<vendor>,<type>", and generic value "jedec,lpddr3".
8 - density : <u32> representing density in Mb (Mega bits)
9 - io-width : <u32> representing bus width. Possible values are 8, 16, 32, 64
10 - #address-cells: Must be set to 1
11 - #size-cells: Must be set to 0
15 - manufacturer-id : <u32> Manufacturer ID value read from Mode Register 5
16 - revision-id : <u32 u32> Revision IDs read from Mode Registers 6 and 7
20 These values shall be obtained from the device data-sheet.
21 - tRFC-min-tck
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H A Djedec,lpddr3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - samsung,K3QF2F20DB
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H A Dlpddr3-timings.txt1 * AC timing parameters of LPDDR3 memories for a given speed-bin.
6 - compatible : Should be "jedec,lpddr3-timings"
7 - min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
8 - reg : maximum DDR clock frequency for the speed-bin. Type is <u32>
13 data-sheet of the device for a given speed-bin. All these properties are
15 - tRFC
16 - tRRD
17 - tRPab
18 - tRPpb
19 - tRCD
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H A Djedec,lpddr3-timings.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr3-timings
19 Maximum DDR clock frequency for the speed-bin, in Hz.
20 Property is deprecated, use max-freq.
23 max-freq:
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/freebsd/sys/contrib/device-tree/Bindings/ddr/
H A Dlpddr3.txt1 * LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C
4 - compatible : Should be "<vendor>,<type>", and generic value "jedec,lpddr3".
8 - density : <u32> representing density in Mb (Mega bits)
9 - io-width : <u32> representing bus width. Possible values are 8, 16, 32, 64
10 - #address-cells: Must be set to 1
11 - #size-cells: Must be set to 0
15 - manufacturer-id : <u32> Manufacturer ID value read from Mode Register 5
16 - revision-id : <u32 u32> Revision IDs read from Mode Registers 6 and 7
20 These values shall be obtained from the device data-sheet.
21 - tRFC-min-tck
[all …]
H A Dlpddr3-timings.txt1 * AC timing parameters of LPDDR3 memories for a given speed-bin.
6 - compatible : Should be "jedec,lpddr3-timings"
7 - min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
8 - reg : maximum DDR clock frequency for the speed-bin. Type is <u32>
13 data-sheet of the device for a given speed-bin. All these properties are
15 - tRFC
16 - tRRD
17 - tRPab
18 - tRPpb
19 - tRCD
[all …]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dnvidia,tegra124-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
18 for DDR3L and LPDDR3 SDRAMs.
22 const: nvidia,tegra124-mc
30 clock-names:
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H A Dnvidia,tegra30-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The EMC interfaces with the off-chip SDRAM to service the request stream
16 sent from Memory Controller. The EMC also has various performance-affecting
19 LPDDR3, and DDR3.
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/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos5422-odroid-core.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source
6 * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd.
10 #include <dt-bindings/clock/samsung,s2mps11.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
14 #include "exynos5422-cpus.dtsi"
27 stdout-path = "serial2:115200n8";
31 compatible = "samsung,secure-firmware";
35 fixed-rate-clocks {
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