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/linux/Documentation/devicetree/bindings/input/
H A Dazoteq,iqs7222.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
21 - azoteq,iqs7222a
22 - azoteq,iqs7222b
23 - azoteq,iqs7222c
24 - azoteq,iqs7222d
29 irq-gpios:
32 Specifies the GPIO connected to the device's active-low RDY output.
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/linux/drivers/net/wireless/mediatek/mt76/mt76x0/
H A Dphy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * (c) Copyright 2002-2010, Ralink Technology, Inc.
26 if (test_bit(MT76_REMOVED, &dev->mphy.state)) in mt76x0_rf_csr_wr()
27 return -ENODEV; in mt76x0_rf_csr_wr()
33 return -EINVAL; in mt76x0_rf_csr_wr()
35 mutex_lock(&dev->phy_mutex); in mt76x0_rf_csr_wr()
38 ret = -ETIMEDOUT; in mt76x0_rf_csr_wr()
50 mutex_unlock(&dev->phy_mutex); in mt76x0_rf_csr_wr()
53 dev_err(dev->mt76.dev, "Error: RF write %d:%d failed:%d!!\n", in mt76x0_rf_csr_wr()
61 int ret = -ETIMEDOUT; in mt76x0_rf_csr_rr()
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/linux/drivers/net/wireless/ath/ath9k/
H A Dar9003_calib.c2 * Copyright (c) 2010-2011 Atheros Communications Inc.
18 #include "hw-ops.h"
44 switch (currCal->calData->calType) { in ar9003_hw_setup_calibration()
52 currCal->calData->calCountMax); in ar9003_hw_setup_calibration()
58 /* Kick-off cal */ in ar9003_hw_setup_calibration()
69 * Recalibrate the lower PHY chips to account for temperature/environment
77 struct ath9k_hw_cal_data *caldata = ah->caldata; in ar9003_hw_per_calibration()
78 const struct ath9k_percal_data *cur_caldata = currCal->calData; in ar9003_hw_per_calibration()
81 if (currCal->calState == CAL_RUNNING) { in ar9003_hw_per_calibration()
87 * Accumulate cal measures for active chains in ar9003_hw_per_calibration()
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H A Dar9003_eeprom.h2 * Copyright (c) 2010-2011 Atheros Communications Inc.
27 /* 16-bit offset location start of calibration struct */
66 * units are: 4 x dBm - NOISE_PWR_DATA_OFFSET
67 * (e.g. -25 = (-25/4 - 90) = -96.25 dBm)
68 * range (for 6 signed bits) is (-32 to 31) + offset => -122dBm to -59dBm
71 #define NOISE_PWR_DATA_OFFSET -90
192 /* takes lower byte in eeprom location */
200 * bit0 - enable tx temp comp
201 * bit1 - enable tx volt comp
202 * bit2 - enable fastClock - default to 1
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H A Dhw.h2 * Copyright (c) 2008-2011 Atheros Communications Inc.
70 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
72 #define ATH_DEFAULT_NOISE_FLOOR -95
74 #define ATH9K_RSSI_BAD -128
80 (_ah)->reg_ops.write((_ah), (_val), (_reg))
83 (_ah)->reg_ops.read((_ah), (_reg))
86 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
89 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
93 if ((_ah)->reg_ops.enable_write_buffer) \
94 (_ah)->reg_ops.enable_write_buffer((_ah)); \
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H A Dar9003_eeprom.c2 * Copyright (c) 2010-2011 Atheros Communications Inc.
36 #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
37 #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
62 .deviceType = 5, /* takes lower byte in eeprom location */
67 * bit0 - enable tx temp comp - disabled
68 * bit1 - enable tx volt comp - disabled
69 * bit2 - enable fastClock - enabled
70 * bit3 - enable doubling - enabled
71 * bit4 - enable internal regulator - disabled
72 * bit5 - enable pa predistortion - disabled
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/linux/drivers/input/misc/
H A Diqs7222.c1 // SPDX-License-Identifier: GPL-2.0-or-later
116 [IQS7222_REG_GRP_CYCLE] = "cycle-%d",
117 [IQS7222_REG_GRP_CHAN] = "channel-%d",
118 [IQS7222_REG_GRP_SLDR] = "slider-%d",
120 [IQS7222_REG_GRP_GPIO] = "gpio-%d",
150 .name = "event-prox",
155 .name = "event-touch",
162 { .name = "event-press", },
164 .name = "event-tap",
171 .name = "event-swipe-pos",
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/linux/drivers/memory/tegra/
H A Dtegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
15 #include <linux/interconnect-provider.h>
512 /* protect shared rate-change code path */
521 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()
522 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()
530 writel(1, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
533 value = readl(emc->regs + EMC_STATUS); in emc_seq_update_timing()
539 dev_err(emc->dev, "timing update timed out\n"); in emc_seq_update_timing()
547 writel(0, emc->regs + EMC_AUTO_CAL_INTERVAL); in emc_seq_disable_auto_cal()
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H A Dtegra30-emc.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
6 * Copyright (C) 2011-2014 NVIDIA Corporation
9 * Copyright (C) 2019 GRATE-DRIVER project
18 #include <linux/interconnect-provider.h>
392 /* protect shared rate-change code path */
403 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
405 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val, in emc_seq_update_timing()
409 dev_err(emc->dev, "failed to update timing: %d\n", err); in emc_seq_update_timing()
422 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
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/linux/drivers/net/wireless/ath/ath5k/
H A Deeprom.c2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
49 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2) in ath5k_eeprom_bin2freq()
52 val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 : in ath5k_eeprom_bin2freq()
55 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2) in ath5k_eeprom_bin2freq()
75 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_init_header()
89 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_0) in ath5k_eeprom_init_header()
101 eep_max = (eep_max | val) - AR5K_EEPROM_INFO_BASE; in ath5k_eeprom_init_header()
114 return -EIO; in ath5k_eeprom_init_header()
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H A Dphy.c2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
5 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
42 * Here we handle the low-level functions related to baseband
48 * - Channel setting/switching
50 * - Automatic Gain Control (AGC) calibration
52 * - Noise Floor calibration
54 * - I/Q imbalance calibration (QAM correction)
56 * - Calibration due to thermal changes (gain_F)
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/linux/drivers/hid/
H A Dhid-nintendo.c1 // SPDX-License-Identifier: GPL-2.0+
3 * HID driver for Nintendo Switch Joy-Cons and Pro Controllers
5 * Copyright (c) 2019-2021 Daniel J. Ogorchock <djogorchock@gmail.com>
12 * https://gitlab.com/pjranki/joycon-linux-kernel (Peter Rankin)
16 * hid-wiimote kernel hid driver
17 * hid-logitech-hidpp driver
18 * hid-sony driver
20 * This driver supports the Nintendo Switch Joy-Cons and Pro Controllers. The
31 #include "hid-ids.h"
120 (JC_CAL_USR_LEFT_DATA_END - JC_CAL_USR_LEFT_DATA_ADDR + 1)
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/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_n.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 /* N-PHY registers. */
18 #define B43_NPHY_4WI_ADDR B43_PHY_N(0x00B) /* Four-wire bus address */
19 #define B43_NPHY_4WI_DATAHI B43_PHY_N(0x00C) /* Four-wire bus data high */
20 #define B43_NPHY_4WI_DATALO B43_PHY_N(0x00D) /* Four-wire bus data low */
21 #define B43_NPHY_BIST_STAT0 B43_PHY_N(0x00E) /* Built-in self test status 0 */
22 #define B43_NPHY_BIST_STAT1 B43_PHY_N(0x00F) /* Built-in self test status 1 */
326 #define B43_NPHY_IQLOCAL_CMD B43_PHY_N(0x0C0) /* I/Q LO cal command */
328 #define B43_NPHY_IQLOCAL_CMDNNUM B43_PHY_N(0x0C1) /* I/Q LO cal command N num */
329 #define B43_NPHY_IQLOCAL_CMDGCTL B43_PHY_N(0x0C2) /* I/Q LO cal command G control */
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/linux/sound/soc/codecs/
H A Dtas2781-fmwlib.c1 // SPDX-License-Identifier: GPL-2.0
3 // tas2781-fmwlib.c -- TASDEVICE firmware support
5 // Copyright 2023 - 2024 Texas Instruments, Inc.
7 // Author: Shenghao Ding <shenghao-ding@ti.com>
43 /*should not include B0_P53_R44-R47 */
158 * receiver, games, audio-to-haptics, PMIC record, bypass mode, in tasdevice_add_config()
161 * ultrasonic application. In order to support these variable-numbers in tasdevice_add_config()
167 *status = -ENOMEM; in tasdevice_add_config()
171 if (tas_priv->rcabin.fw_hdr.binary_version_num >= 0x105) { in tasdevice_add_config()
173 *status = -EINVAL; in tasdevice_add_config()
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/linux/drivers/net/wireless/mediatek/mt7601u/
H A Dphy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * (c) Copyright 2002-2010, Ralink Technology, Inc.
23 if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)) || in mt7601u_rf_wr()
25 return -EINVAL; in mt7601u_rf_wr()
26 if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) in mt7601u_rf_wr()
29 mutex_lock(&dev->reg_atomic_mutex); in mt7601u_rf_wr()
32 ret = -ETIMEDOUT; in mt7601u_rf_wr()
44 mutex_unlock(&dev->reg_atomic_mutex); in mt7601u_rf_wr()
47 dev_err(dev->dev, "Error: RF write %02hhx:%02hhx failed:%d!!\n", in mt7601u_rf_wr()
56 int ret = -ETIMEDOUT; in mt7601u_rf_rr()
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/linux/drivers/net/wireless/intel/iwlegacy/
H A D4965.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
8 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
15 #include <linux/dma-mapping.h>
29 * il_verify_inst_sparse - verify runtime uCode image in card vs. host,
44 /* read data comes through single port, auto-incr addr */ in il4965_verify_inst_sparse()
50 ret = -EIO; in il4965_verify_inst_sparse()
61 * il4965_verify_inst_full - verify runtime uCode image in card vs. host,
77 for (; len > 0; len -= sizeof(u32), image++) { in il4965_verify_inst_full()
78 /* read data comes through single port, auto-incr addr */ in il4965_verify_inst_full()
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H A D3945.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
8 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
16 #include <linux/dma-mapping.h>
94 * il3945_disable_events - Disable selected events in uCode event log
99 * Use for only special debugging. This function is just a placeholder as-is,
107 u32 disable_ptr; /* SRAM address of event-disable bitmap array */ in il3945_disable_events()
110 0x00000000, /* 31 - 0 Event id numbers */ in il3945_disable_events()
111 0x00000000, /* 63 - 32 */ in il3945_disable_events()
112 0x00000000, /* 95 - 64 */ in il3945_disable_events()
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/linux/drivers/mmc/host/
H A Dsdhci-tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
20 #include <linux/mmc/slot-gpio.h>
32 #include "sdhci-cqhci.h"
33 #include "sdhci-pltfm.h"
192 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_readw()
194 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && in tegra_sdhci_readw()
200 return readw(host->ioaddr + reg); in tegra_sdhci_readw()
213 pltfm_host->xfer_mode_shadow = val; in tegra_sdhci_writew()
216 writel((val << 16) | pltfm_host->xfer_mode_shadow, in tegra_sdhci_writew()
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/linux/arch/powerpc/xmon/
H A Dppc-opc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ppc-opc.c -- PowerPC opcode list
3 Copyright (C) 1994-2016 Free Software Foundation, Inc.
27 inserting operands into instructions and vice-versa is kept in this
163 /* The BD field in a B form instruction. The lower two bits are
173 /* The BD field in a B form instruction when the - modifier is used.
179 /* The BD field in a B form instruction when the - modifier is used
224 /* The BO field in a B form instruction when the + or - modifier is
254 { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
268 conditional branch mnemonics, which set the lower two bits of the
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