Lines Matching +full:lower +full:- +full:cal
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
27 /* 16-bit offset location start of calibration struct */
66 * units are: 4 x dBm - NOISE_PWR_DATA_OFFSET
67 * (e.g. -25 = (-25/4 - 90) = -96.25 dBm)
68 * range (for 6 signed bits) is (-32 to 31) + offset => -122dBm to -59dBm
71 #define NOISE_PWR_DATA_OFFSET -90
192 /* takes lower byte in eeprom location */
200 * bit0 - enable tx temp comp
201 * bit1 - enable tx volt comp
202 * bit2 - enable fastClock - default to 1
203 * bit3 - enable doubling - default to 1
204 * bit4 - enable internal regulator - default to 1
207 /* misc flags: bit0 - turn down drivestrength */
261 /* range is -60 to -127 create a mapping equation 1db resolution */
265 /* temp measured when noisefloor cal was performed */
293 * BIT 0 - TX Gain Cap enable.
294 * BIT 1 - Uncompressed Checksum enable.
295 * BIT 2/3 - MinCCApwr enable 2g/5g.