Home
last modified time | relevance | path

Searched full:loads (Results 1 – 25 of 603) sorted by relevance

12345678910>>...25

/linux/tools/perf/pmu-events/arch/powerpc/power8/
H A Dcache.json6 …t Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefe…
12 …t Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefe…
18 … on a different Node or Group (Distant) due to either only demand loads or demand loads plus prefe…
24 …cache was reloaded from local core's L2 due to either only demand loads or demand loads plus prefe…
36 …location other than the local core's L2 due to either only demand loads or demand loads plus prefe…
42 … core's L2 with load hit store conflict due to either only demand loads or demand loads plus prefe…
48 … local core's L2 with dispatch conflict due to either only demand loads or demand loads plus prefe…
54 …ithout dispatch conflicts on Mepf state due to either only demand loads or demand loads plus prefe…
60 …d from local core's L2 without conflict due to either only demand loads or demand loads plus prefe…
66 …cache was reloaded from local core's L3 due to either only demand loads or demand loads plus prefe…
[all …]
H A Dother.json365 … and Final Pump Scope was chip pump (prediction=correct) for either demand loads or data prefetch",
371 … on a different Node or Group (Distant), as this chip due to either demand loads or data prefetch",
372 …t Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefe…
377 … on a different Node or Group (Distant), as this chip due to either demand loads or data prefetch",
378 …t Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefe…
383 …ther chip's L4 on a different Node or Group (Distant) due to either demand loads or data prefetch",
384 … on a different Node or Group (Distant) due to either only demand loads or demand loads plus prefe…
389 …her chip's memory on the same Node or Group (Distant) due to either demand loads or data prefetch",
390 …ory on the same Node or Group (Distant) due to either only demand loads or demand loads plus prefe…
395 …cessor's data cache was reloaded from local core's L2 due to either demand loads or data prefetch",
[all …]
H A Dmemory.json18 …ory on the same Node or Group (Distant) due to either only demand loads or demand loads plus prefe…
24 …s reloaded from the local chip's Memory due to either only demand loads or demand loads plus prefe…
30 …cluding L4 from local remote or distant due to either only demand loads or demand loads plus prefe…
36 … L4 on the same Node or Group ( Remote) due to either only demand loads or demand loads plus prefe…
42 …ory on the same Node or Group ( Remote) due to either only demand loads or demand loads plus prefe…
/linux/tools/perf/pmu-events/arch/x86/ivybridge/
H A Dmemory.json11 "BriefDescription": "Loads with latency value being above 128",
18 "PublicDescription": "Loads with latency value being above 128.",
23 "BriefDescription": "Loads with latency value being above 16",
30 "PublicDescription": "Loads with latency value being above 16.",
35 "BriefDescription": "Loads with latency value being above 256",
42 "PublicDescription": "Loads with latency value being above 256.",
47 "BriefDescription": "Loads with latency value being above 32",
54 "PublicDescription": "Loads with latency value being above 32.",
59 "BriefDescription": "Loads with latency value being above 4",
66 "PublicDescription": "Loads with latency value being above 4.",
[all …]
/linux/tools/perf/pmu-events/arch/x86/tigerlake/
H A Dmemory.json21 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
28 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.",
33 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
40 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.",
45 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
52 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.",
57 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
64 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.",
69 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
76 "PublicDescription": "Counts randomly selected loads whe
[all...]
/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A Dmemory.json85 "BriefDescription": "Randomly selected loads with latency value being above 128",
94 "PublicDescription": "Counts randomly selected loads with latency value being above 128.",
99 "BriefDescription": "Randomly selected loads with latency value being above 16",
108 "PublicDescription": "Counts randomly selected loads with latency value being above 16.",
113 "BriefDescription": "Randomly selected loads with latency value being above 256",
122 "PublicDescription": "Counts randomly selected loads with latency value being above 256.",
127 "BriefDescription": "Randomly selected loads with latency value being above 32",
136 "PublicDescription": "Counts randomly selected loads with latency value being above 32.",
141 "BriefDescription": "Randomly selected loads with latency value being above 4",
150 "PublicDescription": "Counts randomly selected loads wit
[all...]
/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A Dmemory.json11 "BriefDescription": "Loads with latency value being above 128",
18 "PublicDescription": "Loads with latency value being above 128.",
23 "BriefDescription": "Loads with latency value being above 16",
30 "PublicDescription": "Loads with latency value being above 16.",
35 "BriefDescription": "Loads with latency value being above 256",
42 "PublicDescription": "Loads with latency value being above 256.",
47 "BriefDescription": "Loads with latency value being above 32",
54 "PublicDescription": "Loads with latency value being above 32.",
59 "BriefDescription": "Loads with latency value being above 4",
66 "PublicDescription": "Loads with latency value being above 4.",
[all …]
/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A Dmemory.json85 "BriefDescription": "Randomly selected loads with latency value being above 128",
94 "PublicDescription": "Counts randomly selected loads with latency value being above 128.",
99 "BriefDescription": "Randomly selected loads with latency value being above 16",
108 "PublicDescription": "Counts randomly selected loads with latency value being above 16.",
113 "BriefDescription": "Randomly selected loads with latency value being above 256",
122 "PublicDescription": "Counts randomly selected loads with latency value being above 256.",
127 "BriefDescription": "Randomly selected loads with latency value being above 32",
136 "PublicDescription": "Counts randomly selected loads with latency value being above 32.",
141 "BriefDescription": "Randomly selected loads with latency value being above 4",
150 "PublicDescription": "Counts randomly selected loads wit
[all...]
/linux/tools/perf/pmu-events/arch/x86/sandybridge/
H A Dmemory.json12 "BriefDescription": "Loads with latency value being above 128.",
23 "BriefDescription": "Loads with latency value being above 16.",
34 "BriefDescription": "Loads with latency value being above 256.",
45 "BriefDescription": "Loads with latency value being above 32.",
56 "BriefDescription": "Loads with latency value being above 4 .",
67 "BriefDescription": "Loads with latency value being above 512.",
78 "BriefDescription": "Loads with latency value being above 64.",
89 "BriefDescription": "Loads with latency value being above 8.",
112 "EventName": "MISALIGN_MEM_REF.LOADS",
/linux/tools/perf/pmu-events/arch/x86/jaketown/
H A Dmemory.json12 "BriefDescription": "Loads with latency value being above 128.",
23 "BriefDescription": "Loads with latency value being above 16.",
34 "BriefDescription": "Loads with latency value being above 256.",
45 "BriefDescription": "Loads with latency value being above 32.",
56 "BriefDescription": "Loads with latency value being above 4 .",
67 "BriefDescription": "Loads with latency value being above 512.",
78 "BriefDescription": "Loads with latency value being above 64.",
89 "BriefDescription": "Loads with latency value being above 8.",
112 "EventName": "MISALIGN_MEM_REF.LOADS",
/linux/tools/perf/arch/powerpc/util/
H A Dmem-events.c9 E("ldlat-loads", "%s/mem-loads/", "mem-loads", false, 0),
/linux/tools/perf/pmu-events/arch/powerpc/power10/
H A Dothers.json45 … to the latency of the instruction. This includes loads that cross the 128 byte boundary, octword …
50 … to the latency of the instruction. This includes loads that cross the 128 byte boundary, octword …
H A Dmetrics.json390 "BriefDescription": "Percentage of finished loads that missed in the L1",
397 … "BriefDescription": "Percentage of completed instructions that were loads that missed the L1",
471 "BriefDescription": "Average number of finished loads per completed instruction",
477 …"BriefDescription": "Percentage of demand loads that reloaded from the L2 per completed instructio…
484 …"BriefDescription": "Percentage of demand loads that reloaded from beyond the L2 per completed ins…
491 …"BriefDescription": "Percentage of demand loads that reloaded using modified data from another cor…
498 …"BriefDescription": "Percentage of demand loads that reloaded using shared data from another core'…
505 …"BriefDescription": "Percentage of demand loads that reloaded from the L3 per completed instructio…
512 …"BriefDescription": "Percentage of demand loads that reloaded with data brought into the L3 by pre…
519 …"BriefDescription": "Percentage of demand loads that reloaded from beyond the L3 per completed ins…
[all …]
/linux/tools/arch/powerpc/include/asm/
H A Dbarrier.h16 * loads and stores to non-cacheable memory (e.g. I/O devices).
18 * mb() prevents loads and stores being reordered across this point.
19 * rmb() prevents loads being reordered across this point.
/linux/arch/powerpc/include/asm/
H A Dbarrier.h20 * loads and stores to non-cacheable memory (e.g. I/O devices).
22 * mb() prevents loads and stores being reordered across this point.
23 * rmb() prevents loads being reordered across this point.
32 * doesn't order loads with respect to previous stores. Lwsync can be
/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A Dvirtual-memory.json3 "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
7 …"PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TL…
26 …on": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it m…
35 …"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This im…
44 …ption": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies addr…
53 …"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This im…
/linux/tools/perf/pmu-events/arch/x86/skylake/
H A Dvirtual-memory.json7 …"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/…
12 "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
16 …"PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TL…
35 …on": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it m…
44 …"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This im…
53 …ption": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies addr…
62 …"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This im…
/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A Dvirtual-memory.json7 …"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/…
12 "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
16 …"PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TL…
35 …on": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it m…
44 …"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This im…
53 …ption": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies addr…
62 …"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This im…
/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A Dvirtual-memory.json7 …"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/…
12 "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
16 …"PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TL…
35 …on": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it m…
44 …"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This im…
53 …ption": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies addr…
62 …"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This im…
/linux/tools/perf/pmu-events/arch/x86/amdzen1/
H A Dmemory.json23 "BriefDescription": "Counts the number of loads dispatched to the LS unit. Unit Masks ADDed.",
49 "EventName": "ls_mab_alloc.loads",
51 "BriefDescription": "LS MAB allocates by type - loads.",
147 "BriefDescription": "Misaligned loads."
/linux/tools/perf/pmu-events/arch/x86/goldmontplus/
H A Dpipeline.json264 …"BriefDescription": "Loads blocked because address has 4k partial address false dependence (Precis…
269 …"PublicDescription": "Counts loads that block because their address modulo 4K matches a pending st…
274 "BriefDescription": "Loads blocked (Precise event capable)",
284 "BriefDescription": "Loads blocked due to store data not ready (Precise event capable)",
294 … "BriefDescription": "Loads blocked due to store forward restriction (Precise event capable)",
299 …sing a store forward because of an address/size mismatch, only one of the loads blocked from each …
304 … "BriefDescription": "Loads blocked because address in not in the UTLB (Precise event capable)",
309 …"PublicDescription": "Counts loads blocked because they are unable to find their physical address …
335 …at the machines clears due to a page fault. Covers both I-side and D-side(Loads/Stores) page fault…
/linux/tools/perf/pmu-events/arch/x86/haswell/
H A Dmemory.json79 "BriefDescription": "Randomly selected loads with latency value being above 128.",
92 "BriefDescription": "Randomly selected loads with latency value being above 16.",
105 "BriefDescription": "Randomly selected loads with latency value being above 256.",
118 "BriefDescription": "Randomly selected loads with latency value being above 32.",
131 "BriefDescription": "Randomly selected loads with latency value being above 4.",
144 "BriefDescription": "Randomly selected loads with latency value being above 512.",
157 "BriefDescription": "Randomly selected loads with latency value being above 64.",
170 "BriefDescription": "Randomly selected loads with latency value being above 8.",
186 "EventName": "MISALIGN_MEM_REF.LOADS",
H A Dvirtual-memory.json282 "PublicDescription": "Number of DTLB page walker loads that hit in the L1+FB.",
291 "PublicDescription": "Number of DTLB page walker loads that hit in the L2.",
301 "PublicDescription": "Number of DTLB page walker loads that hit in the L3.",
311 "PublicDescription": "Number of DTLB page walker loads from memory.",
384 "PublicDescription": "Number of ITLB page walker loads that hit in the L1+FB.",
393 "PublicDescription": "Number of ITLB page walker loads that hit in the L2.",
403 "PublicDescription": "Number of ITLB page walker loads that hit in the L3.",
413 "PublicDescription": "Number of ITLB page walker loads from memory.",
/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A Dvirtual-memory.json282 "PublicDescription": "Number of DTLB page walker loads that hit in the L1+FB.",
291 "PublicDescription": "Number of DTLB page walker loads that hit in the L2.",
301 "PublicDescription": "Number of DTLB page walker loads that hit in the L3.",
311 "PublicDescription": "Number of DTLB page walker loads from memory.",
384 "PublicDescription": "Number of ITLB page walker loads that hit in the L1+FB.",
393 "PublicDescription": "Number of ITLB page walker loads that hit in the L2.",
403 "PublicDescription": "Number of ITLB page walker loads that hit in the L3.",
413 "PublicDescription": "Number of ITLB page walker loads from memory.",
/linux/arch/mips/include/asm/octeon/
H A Docteon.h222 * loads/stores can use XKPHYS addresses with
225 /* R/W If set (and UX set), user-level loads/stores
229 * loads/stores can use XKPHYS addresses with
232 /* R/W If set (and UX set), user-level loads/stores
265 /* R/W If set, CVMSEG is available for loads/stores in
268 /* R/W If set, CVMSEG is available for loads/stores in
271 /* R/W If set, CVMSEG is available for loads/stores in

12345678910>>...25