| /linux/tools/testing/selftests/powerpc/ptrace/ |
| H A D | ptrace-vsx.h | 11 * unsigned long load[128]
13 int validate_vsx(unsigned long *vsx, unsigned long *load) in validate_vsx() argument
18 if (vsx[i] != load[2 * i + 1]) { in validate_vsx()
19 printf("vsx[%d]: %lx load[%d] %lx\n", in validate_vsx()
20 i, vsx[i], 2 * i + 1, load[2 * i + 1]); in validate_vsx()
29 * unsigned long load[128]
31 int validate_vmx(unsigned long vmx[][2], unsigned long *load) in validate_vmx() argument
37 if ((vmx[i][0] != load[64 + 2 * i]) || in validate_vmx()
38 (vmx[i][1] != load[65 + 2 * i])) { in validate_vmx()
39 printf("vmx[%d][0]: %lx load[%d] %lx\n", in validate_vmx()
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| /linux/arch/alpha/include/asm/ |
| H A D | xor.h | 73 xor $0,$1,$0 # 7 cycles from $1 load \n\
130 xor $0,$1,$1 # 8 cycles from $0 load \n\
131 xor $3,$4,$4 # 6 cycles from $4 load \n\
132 xor $6,$7,$7 # 6 cycles from $7 load \n\
133 xor $21,$22,$22 # 5 cycles from $22 load \n\
135 xor $1,$2,$2 # 9 cycles from $2 load \n\
136 xor $24,$25,$25 # 5 cycles from $25 load \n\
138 xor $4,$5,$5 # 6 cycles from $5 load \n\
141 xor $7,$20,$20 # 7 cycles from $20 load \n\
143 xor $22,$23,$23 # 7 cycles from $23 load \n\
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| /linux/tools/power/cpupower/bench/ |
| H A D | README-BENCH | 9 - Identify average reaction time of a governor to CPU load changes
34 You can specify load (100% CPU load) and sleep (0% CPU load) times in us which
38 load=25000
41 This part of the configuration file will create 25ms load/sleep turns,
48 Will increase load and sleep time by 25ms 5 times.
50 25ms load/sleep time repeated 20 times (cycles).
51 50ms load/sleep time repeated 20 times (cycles).
53 100ms load/sleep time repeated 20 times (cycles).
69 100% CPU load (load) | 0 % CPU load (sleep) | round
76 In round 1, ondemand should have rather static 50% load and probably
[all …]
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| H A D | benchmark.c | 25 * to get the given load time
27 * @param load aimed load time in µs
32 unsigned int calculate_timespace(long load, struct config *config) in calculate_timespace() argument
41 printf("calibrating load of %lius, please wait...\n", load); in calculate_timespace()
50 /* approximation of the wanted load time by comparing with the in calculate_timespace()
53 rounds = (unsigned int)(load * estimated / timed); in calculate_timespace()
70 * generates a specific sleep an load time with the performance
88 load_time = config->load; in start_benchmark()
92 total_time += _round * (config->sleep + config->load); in start_benchmark()
107 * _rounds should produce a load which matches the configured in start_benchmark()
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| /linux/include/linux/ |
| H A D | hp_sdc.h | 175 #define HP_SDC_CMD_LOAD_RT 0x31 /* Load real time (from 8042) */
176 #define HP_SDC_CMD_LOAD_FHS 0x36 /* Load the fast handshake timer */
177 #define HP_SDC_CMD_LOAD_MT 0x38 /* Load the match timer */
178 #define HP_SDC_CMD_LOAD_DT 0x3B /* Load the delay timer */
179 #define HP_SDC_CMD_LOAD_CT 0x3E /* Load the cycle timer */
187 #define HP_SDC_CMD_READ_RAM 0x00 /* Load from i8042 RAM (autoinc) */
188 #define HP_SDC_CMD_READ_USE 0x02 /* Undocumented! Load from usage reg */
189 #define HP_SDC_CMD_READ_IM 0x04 /* Load current interrupt mask */
190 #define HP_SDC_CMD_READ_KCC 0x11 /* Load primary kbd config code */
191 #define HP_SDC_CMD_READ_KLC 0x12 /* Load primary kbd language code */
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| /linux/tools/perf/pmu-events/arch/powerpc/power8/ |
| H A D | memory.json | 5 …p (prediction=correct) for all data types excluding data prefetch (demand load,inst prefetch,inst …
6 …this scope was chip pump (prediction=correct) for all data types ( demand load,data,inst prefetch,…
11 …fDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load",
12 …Pump Scope and data sourced across this scope was chip pump (prediction=correct) for a demand load"
17 … was reloaded from another chip's memory on the same Node or Group (Distant) due to a demand load",
23 …tion": "The processor's data cache was reloaded from the local chip's Memory due to a demand load",
29 …as reloaded from a memory location including L4 from local remote or distant due to a demand load",
35 …ache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a demand load",
41 … was reloaded from another chip's memory on the same Node or Group ( Remote) due to a demand load",
47 …Description": "Initial and Final Pump Scope was group pump (prediction=correct) for a demand load",
[all …]
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| H A D | marked.json | 35 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
41 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
47 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
53 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
59 …e was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load",
65 …cles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load",
71 … was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load",
77 …les to reload from another chip's memory on the same Node or Group (Distant) due to a marked load",
83 …fDescription": "The processor's data cache was reloaded from local core's L2 due to a marked load",
95 …"Duration in cycles to reload from a location other than the local core's L2 due to a marked load",
[all …]
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| H A D | cache.json | 5 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
11 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
17 …e was reloaded from another chip's L4 on a different Node or Group (Distant) due to a demand load",
23 …fDescription": "The processor's data cache was reloaded from local core's L2 due to a demand load",
35 …sor's data cache was reloaded from a location other than the local core's L2 due to a demand load",
41 …r's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load…
42 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 with load hit s…
47 …cessor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load",
53 …s reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load",
59 …he processor's data cache was reloaded from local core's L2 without conflict due to a demand load",
[all …]
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| H A D | metrics.json | 297 "BriefDescription": "Cycles stalled by LSU load finishes",
492 …"BriefDescription": "Percentage of L2 load hits per instruction where the L2 experienced a Load-Hi…
504 …"BriefDescription": "Percentage of L2 load hits per instruction where the L2 did not experience a …
510 …riefDescription": "Percentage of L2 load hits per instruction where the L2 experienced some confli…
534 …"BriefDescription": "Percentage of L3 load hits per instruction where the load collided with a pen…
546 …"BriefDescription": "Percentage of L3 load hits per instruction where the L3 did not experience a …
594 "BriefDescription": "Percentage of L1 demand load misses per run instruction",
642 "BriefDescription": "Percentage of DL1 reloads from L2 with a Load-Hit-Store conflict",
654 …"BriefDescription": "Percentage of DL1 reloads from L2 with some conflict other than Load-Hit-Stor…
678 …"BriefDescription": "Percentage of DL1 reloads from L3 where the load collided with a pending pref…
[all …]
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| /linux/arch/sparc/lib/ |
| H A D | csum_copy.S | 27 #ifndef LOAD
28 #define LOAD(type,addr,dest) type [addr], dest macro
50 EX_LD(LOAD(ldub, %o0 + 0x00, %o4))
60 EX_LD(LOAD(lduh, %o0 + 0x00, %o5))
72 LOAD(prefetch, %o0 + 0x000, #n_reads)
78 LOAD(prefetch, %o0 + 0x040, #n_reads)
91 LOAD(prefetch, %o0 + 0x080, #n_reads)
94 LOAD(prefetch, %o0 + 0x0c0, #n_reads)
97 LOAD(prefetch, %o0 + 0x100, #n_reads)
105 LOAD(prefetch, %o0 + 0x140, #n_reads)
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| H A D | NG2memcpy.S | 50 #ifndef LOAD
51 #define LOAD(type,addr,dest) type [addr], dest macro
141 EX_LD_FP(LOAD(ldd, base + 0x00, %x0), NG2_retl_o2_plus_g1)
143 EX_LD_FP(LOAD(ldd, base + 0x00, %x0), NG2_retl_o2_plus_g1); \
144 EX_LD_FP(LOAD(ldd, base + 0x08, %x1), NG2_retl_o2_plus_g1);
146 EX_LD_FP(LOAD(ldd, base + 0x00, %x0), NG2_retl_o2_plus_g1); \
147 EX_LD_FP(LOAD(ldd, base + 0x08, %x1), NG2_retl_o2_plus_g1); \
148 EX_LD_FP(LOAD(ldd, base + 0x10, %x2), NG2_retl_o2_plus_g1);
150 EX_LD_FP(LOAD(ldd, base + 0x00, %x0), NG2_retl_o2_plus_g1); \
151 EX_LD_FP(LOAD(ldd, base + 0x08, %x1), NG2_retl_o2_plus_g1); \
[all …]
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| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/ |
| H A D | pipeline.json | 27 …re is an interlock. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded",
30 …ere is an interlock. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded"
33 …due to a load/store instruction waiting for data to calculate the address in the AGU. Stall cycles…
36 …due to a load/store instruction waiting for data to calculate the address in the AGU. Stall cycles…
39 …truction. Stall cycles due to a stall in the Wr stage (typically awaiting load data) are excluded",
42 …struction. Stall cycles due to a stall in the Wr stage (typically awaiting load data) are excluded"
45 …peration issued due to the backend, load.This event counts every cycle there is a stall in the Wr …
48 …peration issued due to the backend, load.This event counts every cycle there is a stall in the Wr …
57 …on issued due to the backend, load, cache miss.This event counts every cycle there is a stall in t…
60 …on issued due to the backend, load, cache miss.This event counts every cycle there is a stall in t…
[all …]
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| /linux/arch/mips/cavium-octeon/ |
| H A D | octeon-memcpy.S | 46 * When an exception happens on a load, the handler must
84 #define LOAD ld macro
187 EXC( LOAD t0, UNIT(0)(src), l_exc)
188 EXC( LOAD t1, UNIT(1)(src), l_exc_copy)
189 EXC( LOAD t2, UNIT(2)(src), l_exc_copy)
190 EXC( LOAD t3, UNIT(3)(src), l_exc_copy)
196 EXC( LOAD t0, UNIT(4)(src), l_exc_copy)
197 EXC( LOAD t1, UNIT(5)(src), l_exc_copy)
198 EXC( LOAD t2, UNIT(6)(src), l_exc_copy)
199 EXC( LOAD t3, UNIT(7)(src), l_exc_copy)
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| /linux/tools/perf/pmu-events/arch/x86/grandridge/ |
| H A D | memory.json | 3 …load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, …
11 …dest load) of the load buffer is stalled due to a core bound stall including a store address match…
19 …"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer an…
27 …"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer an…
31 …"PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer a…
36 …"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer an…
44 …"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer an…
|
| /linux/tools/perf/pmu-events/arch/x86/clearwaterforest/ |
| H A D | cache.json | 21 "BriefDescription": "Counts the number of load ops retired.",
25 "PublicDescription": "Counts the number of load ops retired. Available PDIST counters: 0,1",
39 …"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency thresho…
45 …"PublicDescription": "Counts the number of tagged load uops retired that exceed the latency thresh…
50 …"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency thresho…
56 …"PublicDescription": "Counts the number of tagged load uops retired that exceed the latency thresh…
61 …"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency thresho…
67 …"PublicDescription": "Counts the number of tagged load uops retired that exceed the latency thresh…
72 …"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency thresho…
78 …"PublicDescription": "Counts the number of tagged load uops retired that exceed the latency thresh…
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/arrowlake/ |
| H A D | memory.json | 3 …load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, …
12 …load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, …
21 …dest load) of the load buffer is stalled due to a core bound stall including a store address match…
30 …dest load) of the load buffer is stalled due to a core bound stall including a store address match…
39 …"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is…
48 …"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer an…
57 …"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer an…
66 …"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer an…
70 …"PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer a…
76 …"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer an…
[all …]
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| H A D | cache.json | 12 …"BriefDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, s…
16 …"PublicDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, …
46 …(FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW …
56 …ack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW …
65 "EventName": "L1D_MISS.LOAD",
75 "EventName": "L1D_PENDING.LOAD",
82 "BriefDescription": "Cycles with L1D load Misses outstanding.",
303 …"PublicDescription": "Counts the number of demand Data Read requests initiated by load instruction…
446 …n": "Counts the number of unhalted cycles when the core is stalled due to an L1 demand load miss.",
455 …n": "Counts the number of unhalted cycles when the core is stalled due to an L1 demand load miss.",
[all …]
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| /linux/arch/powerpc/lib/ |
| H A D | xor_vmx.c | 28 #define LOAD(V) \ macro
61 LOAD(v1); in __xor_altivec_2()
62 LOAD(v2); in __xor_altivec_2()
82 LOAD(v1); in __xor_altivec_3()
83 LOAD(v2); in __xor_altivec_3()
84 LOAD(v3); in __xor_altivec_3()
108 LOAD(v1); in __xor_altivec_4()
109 LOAD(v2); in __xor_altivec_4()
110 LOAD(v3); in __xor_altivec_4()
111 LOAD(v4); in __xor_altivec_4()
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/sierraforest/ |
| H A D | memory.json | 3 …load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, …
11 …dest load) of the load buffer is stalled due to a core bound stall including a store address match…
19 …"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer an…
27 …"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer an…
31 …"PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer a…
36 …"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer an…
44 …"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer an…
|
| /linux/tools/perf/pmu-events/arch/powerpc/power9/ |
| H A D | other.json | 45 …ssor's data cache was reloaded from a location other than the local core's L3 due to a marked load"
60 …"BriefDescription": "A demand load referenced a line in an active fuzzy prefetch stream. The strea…
135 …n an enabled section of the Load Monitored region. This event, therefore, should not occur if the…
145 …r's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load"
170 "BriefDescription": "Load tm hit in L1"
205 … to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load"
225 …cles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load"
230 "BriefDescription": "Duration in cycles to reload from local core's L2 due to a marked load"
235 … "BriefDescription": "Core TM load hits line in L3 in TM_SC state and causes it to be invalidated"
255 …r's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load"
[all …]
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| /linux/tools/perf/Documentation/ |
| H A D | perf-c2c.txt | 22 On Intel, the tool is based on load latency and precise store facility events
26 sample load and store operations, therefore hardware and kernel support is
33 - type of the access (load and store details)
34 - latency (in cycles) of the load access
65 - Load latency filtering is disabled by default.
208 LLC Load Hitm - Total, LclHitm, RmtHitm (For display with HITM types)
209 - count of Total/Local/Remote load HITMs
211 Load Peer - Total, Local, Remote (For display with peer type)
212 - count of Total/Local/Remote load from peer cache or DRAM
218 - sum of all load accesses
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| /linux/Documentation/ |
| H A D | memory-barriers.txt | 59 - Read memory barriers vs load speculation.
158 STORE A=3, STORE B=4, y=LOAD A->3, x=LOAD B->4
159 STORE A=3, STORE B=4, x=LOAD B->4, y=LOAD A->3
160 STORE A=3, y=LOAD A->3, STORE B=4, x=LOAD B->4
161 STORE A=3, y=LOAD A->3, x=LOAD B->2, STORE B=4
162 STORE A=3, x=LOAD B->2, STORE B=4, y=LOAD A->3
163 STORE A=3, x=LOAD B->2, y=LOAD A->3, STORE B=4
164 STORE B=4, STORE A=3, y=LOAD A->3, x=LOAD B->4
197 Note that CPU 2 will never try and load C into D because the CPU will load P
198 into Q before issuing the load of *Q.
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| /linux/net/core/ |
| H A D | ptp_classifier.c | 12 * ldh [12] ; load ethertype
17 * ldb [23] ; load proto
19 * ldh [20] ; load frag offset field
21 * ldxb 4*([14]&0xf) ; load IP header len
22 * ldh [x + 16] ; load UDP dst port
24 * ldh [x + 22] ; load payload
33 * ldb [20] ; load proto
35 * ldh [56] ; load UDP dst port
37 * ldh [62] ; load payload
46 * ldh [16] ; load inner type
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| /linux/tools/perf/pmu-events/arch/powerpc/power10/ |
| H A D | others.json | 35 "BriefDescription": "256-bit load finished in the LD0 load execution unit."
40 "BriefDescription": "256-bit load finished in the LD1 load execution unit."
45 …Load instructions in LD0 port that are either unaligned, or treated as unaligned and require an ad…
50 …Load instructions in LD1 port that are either unaligned, or treated as unaligned and require an ad…
65 …"BriefDescription": "A demand load referenced a line in an active strided prefetch stream. The str…
|
| /linux/arch/powerpc/include/asm/ |
| H A D | xive-regs.h | 25 * load instruction. They all return the previous state of the
33 #define XIVE_ESB_LOAD_EOI 0x000 /* Load */
34 #define XIVE_ESB_GET 0x800 /* Load */
35 #define XIVE_ESB_SET_PQ_00 0xc00 /* Load */
36 #define XIVE_ESB_SET_PQ_01 0xd00 /* Load */
37 #define XIVE_ESB_SET_PQ_10 0xe00 /* Load */
38 #define XIVE_ESB_SET_PQ_11 0xf00 /* Load */
41 * Load-after-store ordering
43 * Adding this offset to the load address will enforce
44 * load-after-store ordering. This is required to use StoreEOI.
[all …]
|