| /linux/drivers/gpu/drm/radeon/ |
| H A D | rv730_dpm.c | 244 &table->ACPIState.levels[0].vddc); in rv730_populate_smc_acpi_state()
245 table->ACPIState.levels[0].gen2PCIE = pi->pcie_gen2 ? in rv730_populate_smc_acpi_state()
247 table->ACPIState.levels[0].gen2XSP = in rv730_populate_smc_acpi_state()
251 &table->ACPIState.levels[0].vddc); in rv730_populate_smc_acpi_state()
252 table->ACPIState.levels[0].gen2PCIE = 0; in rv730_populate_smc_acpi_state()
294 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); in rv730_populate_smc_acpi_state()
295 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2); in rv730_populate_smc_acpi_state()
296 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3); in rv730_populate_smc_acpi_state()
297 table->ACPIState.levels[0].mclk.mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in rv730_populate_smc_acpi_state()
298 table->ACPIState.levels[0].mclk.mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl); in rv730_populate_smc_acpi_state()
[all …]
|
| H A D | rv740_dpm.c | 337 &table->ACPIState.levels[0].vddc); in rv740_populate_smc_acpi_state()
338 table->ACPIState.levels[0].gen2PCIE = in rv740_populate_smc_acpi_state()
341 table->ACPIState.levels[0].gen2XSP = in rv740_populate_smc_acpi_state()
345 &table->ACPIState.levels[0].vddc); in rv740_populate_smc_acpi_state()
346 table->ACPIState.levels[0].gen2PCIE = 0; in rv740_populate_smc_acpi_state()
376 table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in rv740_populate_smc_acpi_state()
377 table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); in rv740_populate_smc_acpi_state()
378 table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in rv740_populate_smc_acpi_state()
379 table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); in rv740_populate_smc_acpi_state()
380 table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in rv740_populate_smc_acpi_state()
[all …]
|
| H A D | cypress_dpm.c | 778 &smc_state->levels[0], in cypress_convert_power_state_to_smc()
785 &smc_state->levels[1], in cypress_convert_power_state_to_smc()
792 &smc_state->levels[2], in cypress_convert_power_state_to_smc()
797 smc_state->levels[0].arbValue = MC_CG_ARB_FREQ_F1; in cypress_convert_power_state_to_smc()
798 smc_state->levels[1].arbValue = MC_CG_ARB_FREQ_F2; in cypress_convert_power_state_to_smc()
799 smc_state->levels[2].arbValue = MC_CG_ARB_FREQ_F3; in cypress_convert_power_state_to_smc()
802 smc_state->levels[0].ACIndex = 2; in cypress_convert_power_state_to_smc()
803 smc_state->levels[1].ACIndex = 3; in cypress_convert_power_state_to_smc()
804 smc_state->levels[2].ACIndex = 4; in cypress_convert_power_state_to_smc()
806 smc_state->levels[0].ACIndex = 0; in cypress_convert_power_state_to_smc()
[all …]
|
| /linux/drivers/video/backlight/ |
| H A D | pwm_bl.c | 25 unsigned int *levels; member
80 if (pb->levels) in compute_duty_cycle()
81 duty_cycle = pb->levels[brightness]; in compute_duty_cycle()
190 * Once we have 4096 levels there's little point going much higher... in pwm_backlight_brightness_default()
197 data->levels = devm_kcalloc(dev, data->max_brightness, in pwm_backlight_brightness_default()
198 sizeof(*data->levels), GFP_KERNEL); in pwm_backlight_brightness_default()
199 if (!data->levels) in pwm_backlight_brightness_default()
209 data->levels[i] = (unsigned int)retval; in pwm_backlight_brightness_default()
244 * Determine the number of brightness levels, if this property is not in pwm_backlight_parse_dt()
245 * set a default table of brightness levels will be used. in pwm_backlight_parse_dt()
[all …]
|
| H A D | led_bl.c | 20 unsigned int *levels; member
30 if (priv->levels) in led_bl_set_brightness()
31 bkl_brightness = priv->levels[level]; in led_bl_set_brightness()
134 num_levels = of_property_count_u32_elems(node, "brightness-levels"); in led_bl_parse_levels()
138 u32 *levels = NULL; in led_bl_parse_levels() local
140 levels = devm_kzalloc(dev, sizeof(u32) * num_levels, in led_bl_parse_levels()
142 if (!levels) in led_bl_parse_levels()
145 ret = of_property_read_u32_array(node, "brightness-levels", in led_bl_parse_levels()
146 levels, in led_bl_parse_levels()
157 if ((i && db > levels[i-1]) && db <= levels[i]) in led_bl_parse_levels()
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/broadwellx/ |
| H A D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
8 …"PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of an…
37 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
46 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
51 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
56 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
61 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
66 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
71 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
86 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/broadwellde/ |
| H A D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
8 …"PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of an…
37 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
46 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
51 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
56 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
61 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
66 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
71 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
86 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/broadwell/ |
| H A D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
8 …"PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of an…
37 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
46 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
51 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
56 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
61 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
66 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
71 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
86 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/skylake/ |
| H A D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
7 …e walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need…
31 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
35 …sed by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page w…
44 … loads. This implies address translations missed in the DTLB and further levels of TLB. The page w…
53 … loads. This implies address translations missed in the DTLB and further levels of TLB. The page w…
62 … loads. This implies address translations missed in the DTLB and further levels of TLB. The page w…
76 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
80 …e walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need…
104 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/skylakex/ |
| H A D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
7 …e walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need…
31 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
35 …sed by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page w…
44 … loads. This implies address translations missed in the DTLB and further levels of TLB. The page w…
53 … loads. This implies address translations missed in the DTLB and further levels of TLB. The page w…
62 … loads. This implies address translations missed in the DTLB and further levels of TLB. The page w…
76 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
80 …e walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need…
104 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| H A D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
7 …e walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need…
31 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
35 …sed by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page w…
44 … loads. This implies address translations missed in the DTLB and further levels of TLB. The page w…
53 … loads. This implies address translations missed in the DTLB and further levels of TLB. The page w…
62 … loads. This implies address translations missed in the DTLB and further levels of TLB. The page w…
76 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
80 …e walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need…
104 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
[all …]
|
| /linux/arch/powerpc/platforms/powernv/ |
| H A D | pci-ioda-tce.c | 81 unsigned long size, unsigned int levels);
217 unsigned long size, unsigned int levels) in pnv_pci_ioda2_table_do_free_pages() argument
222 if (levels) { in pnv_pci_ioda2_table_do_free_pages()
233 levels - 1); in pnv_pci_ioda2_table_do_free_pages()
257 unsigned int levels, unsigned long limit, in pnv_pci_ioda2_table_do_alloc_pages() argument
268 --levels; in pnv_pci_ioda2_table_do_alloc_pages()
269 if (!levels) { in pnv_pci_ioda2_table_do_alloc_pages()
276 levels, limit, current_offset, total_allocated); in pnv_pci_ioda2_table_do_alloc_pages()
291 __u32 page_shift, __u64 window_size, __u32 levels, in pnv_pci_ioda2_table_alloc_pages() argument
303 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) in pnv_pci_ioda2_table_alloc_pages()
[all …]
|
| /linux/Documentation/scheduler/ |
| H A D | sched-nice-design.rst | 6 nice-levels implementation in the new Linux scheduler.
8 Nice levels were always pretty weak under Linux and people continuously
16 In the O(1) scheduler (in 2003) we changed negative nice levels to be
58 To sum it up: we always wanted to make nice levels more consistent, but
83 nice levels were not 'punchy enough', so lots of people had to resort to
90 To address the first complaint (of nice levels being not "punchy"
92 (and granularity was made a separate concept from nice levels) and thus
98 To address the second complaint (of nice levels not being consistent),
100 tasks, regardless of their absolute nice levels. So on the new
104 levels were changed to be "multiplicative" (or exponential) - that way
[all …]
|
| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ |
| H A D | r535.c | 71 ctrl->levels[0].physAddress = vmm->pd->pt[0]->addr; in r535_mmu_promote_vmm()
72 ctrl->levels[0].size = 0x20; in r535_mmu_promote_vmm()
73 ctrl->levels[0].aperture = 1; in r535_mmu_promote_vmm()
74 ctrl->levels[0].pageShift = 0x2f; in r535_mmu_promote_vmm()
75 ctrl->levels[1].physAddress = vmm->pd->pde[0]->pt[0]->addr; in r535_mmu_promote_vmm()
76 ctrl->levels[1].size = 0x1000; in r535_mmu_promote_vmm()
77 ctrl->levels[1].aperture = 1; in r535_mmu_promote_vmm()
78 ctrl->levels[1].pageShift = 0x26; in r535_mmu_promote_vmm()
80 ctrl->levels[2].physAddress = vmm->pd->pde[0]->pde[0]->pt[0]->addr; in r535_mmu_promote_vmm()
81 ctrl->levels[2].size = 0x1000; in r535_mmu_promote_vmm()
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/emeraldrapids/ |
| H A D | virtual-memory.json | 22 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
26 …sed by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page w…
35 … loads. This implies address translations missed in the DTLB and further levels of TLB. The page w…
44 … loads. This implies address translations missed in the DTLB and further levels of TLB. The page w…
53 … loads. This implies address translations missed in the DTLB and further levels of TLB. The page w…
86 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
90 …ed by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page w…
99 …stores. This implies address translations missed in the DTLB and further levels of TLB. The page w…
108 …stores. This implies address translations missed in the DTLB and further levels of TLB. The page w…
117 …stores. This implies address translations missed in the DTLB and further levels of TLB. The page w…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| H A D | virtual-memory.json | 22 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
26 …sed by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page w…
35 … loads. This implies address translations missed in the DTLB and further levels of TLB. The page w…
44 … loads. This implies address translations missed in the DTLB and further levels of TLB. The page w…
53 … loads. This implies address translations missed in the DTLB and further levels of TLB. The page w…
86 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
90 …ed by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page w…
99 …stores. This implies address translations missed in the DTLB and further levels of TLB. The page w…
108 …stores. This implies address translations missed in the DTLB and further levels of TLB. The page w…
117 …stores. This implies address translations missed in the DTLB and further levels of TLB. The page w…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/graniterapids/ |
| H A D | virtual-memory.json | 22 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
26 …sed by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page w…
35 … loads. This implies address translations missed in the DTLB and further levels of TLB. The page w…
44 … loads. This implies address translations missed in the DTLB and further levels of TLB. The page w…
53 … loads. This implies address translations missed in the DTLB and further levels of TLB. The page w…
86 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
90 …ed by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page w…
99 …stores. This implies address translations missed in the DTLB and further levels of TLB. The page w…
108 …stores. This implies address translations missed in the DTLB and further levels of TLB. The page w…
117 …stores. This implies address translations missed in the DTLB and further levels of TLB. The page w…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/ivytown/ |
| H A D | virtual-memory.json | 3 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
27 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes an p…
31 …"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand…
45 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
49 …"PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by dema…
63 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
67 … "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).",
81 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
85 …"PublicDescription": "Miss in all TLB levels causes a page walk that completes of any page size (4…
125 "BriefDescription": "Misses at all ITLB levels that cause page walks",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/ivybridge/ |
| H A D | virtual-memory.json | 11 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes an p…
15 …"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand…
29 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
33 …"PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by dema…
47 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
51 … "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).",
65 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
69 …"PublicDescription": "Miss in all TLB levels causes a page walk that completes of any page size (4…
109 "BriefDescription": "Misses at all ITLB levels that cause page walks",
113 "PublicDescription": "Misses in all ITLB levels that cause page walks.",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/alderlake/ |
| H A D | virtual-memory.json | 28 …se address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to…
34 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
38 …sed by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page w…
48 … loads. This implies address translations missed in the DTLB and further levels of TLB. The page w…
58 … loads. This implies address translations missed in the DTLB and further levels of TLB. The page w…
68 … loads. This implies address translations missed in the DTLB and further levels of TLB. The page w…
109 …se address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to…
115 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
119 …ed by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page w…
129 …stores. This implies address translations missed in the DTLB and further levels of TLB. The page w…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/icelakex/ |
| H A D | virtual-memory.json | 22 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
26 …sed by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page w…
35 … loads. This implies address translations missed in the DTLB and further levels of TLB. The page w…
44 … loads. This implies address translations missed in the DTLB and further levels of TLB. The page w…
53 … loads. This implies address translations missed in the DTLB and further levels of TLB. The page w…
86 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
90 …ed by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page w…
99 …stores. This implies address translations missed in the DTLB and further levels of TLB. The page w…
108 …stores. This implies address translations missed in the DTLB and further levels of TLB. The page w…
117 …stores. This implies address translations missed in the DTLB and further levels of TLB. The page w…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/lunarlake/ |
| H A D | virtual-memory.json | 7 …se address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to…
13 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
17 …sed by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page w…
27 …se address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to…
33 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
37 …ed by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page w…
47 …se address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to…
53 …"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page size…
57 … fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page w…
|
| /linux/tools/perf/pmu-events/arch/x86/haswell/ |
| H A D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
7 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.",
48 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
57 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
65 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
69 …: "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.",
74 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
78 …on": "Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.",
92 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
96 … "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/haswellx/ |
| H A D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
7 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.",
48 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
57 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
65 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
69 …: "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.",
74 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
78 …on": "Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.",
92 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
96 … "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/meteorlake/ |
| H A D | virtual-memory.json | 42 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
46 …sed by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page w…
56 … loads. This implies address translations missed in the DTLB and further levels of TLB. The page w…
66 …se address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to…
76 … loads. This implies address translations missed in the DTLB and further levels of TLB. The page w…
86 …se address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to…
96 … loads. This implies address translations missed in the DTLB and further levels of TLB. The page w…
161 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
165 …ed by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page w…
175 …stores. This implies address translations missed in the DTLB and further levels of TLB. The page w…
[all …]
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