345 	u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk;  in sumo_program_bsp()
409 		m_a = asi * ps->levels[i].sclk / 100;  in sumo_program_at()
668 		pi->boost_pl = new_ps->levels[new_ps->num_levels - 1];  in sumo_patch_boost_state()
760 		sumo_program_power_level(rdev, &new_ps->levels[i], i);  in sumo_program_power_levels_0_to_n()
842 	if (new_ps->levels[new_ps->num_levels - 1].sclk >=  in sumo_set_uvd_clock_before_set_eng_clock()
843 	    current_ps->levels[current_ps->num_levels - 1].sclk)  in sumo_set_uvd_clock_before_set_eng_clock()
860 	if (new_ps->levels[new_ps->num_levels - 1].sclk <  in sumo_set_uvd_clock_after_set_eng_clock()
861 	    current_ps->levels[current_ps->num_levels - 1].sclk)  in sumo_set_uvd_clock_after_set_eng_clock()
1051 		current_vddc = current_ps->levels[current_index].vddc_index;  in sumo_patch_thermal_state()
1052 		current_sclk = current_ps->levels[current_index].sclk;  in sumo_patch_thermal_state()
1058 	ps->levels[0].vddc_index = current_vddc;  in sumo_patch_thermal_state()
1060 	if (ps->levels[0].sclk > current_sclk)  in sumo_patch_thermal_state()
1061 		ps->levels[0].sclk = current_sclk;  in sumo_patch_thermal_state()
1063 	ps->levels[0].ss_divider_index =  in sumo_patch_thermal_state()
1064 		sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, sclk_in_sr);  in sumo_patch_thermal_state()
1066 	ps->levels[0].ds_divider_index =  in sumo_patch_thermal_state()
1067 		sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, SUMO_MINIMUM_ENGINE_CLOCK);  in sumo_patch_thermal_state()
1069 	if (ps->levels[0].ds_divider_index > ps->levels[0].ss_divider_index + 1)  in sumo_patch_thermal_state()
1070 		ps->levels[0].ds_divider_index = ps->levels[0].ss_divider_index + 1;  in sumo_patch_thermal_state()
1072 	if (ps->levels[0].ss_divider_index == ps->levels[0].ds_divider_index) {  in sumo_patch_thermal_state()
1073 		if (ps->levels[0].ss_divider_index > 1)  in sumo_patch_thermal_state()
1074 			ps->levels[0].ss_divider_index = ps->levels[0].ss_divider_index - 1;  in sumo_patch_thermal_state()
1077 	if (ps->levels[0].ss_divider_index == 0)  in sumo_patch_thermal_state()
1078 		ps->levels[0].ds_divider_index = 0;  in sumo_patch_thermal_state()
1080 	if (ps->levels[0].ds_divider_index == 0)  in sumo_patch_thermal_state()
1081 		ps->levels[0].ss_divider_index = 0;  in sumo_patch_thermal_state()
1110 		if (ps->levels[i].vddc_index < min_voltage)  in sumo_apply_state_adjust_rules()
1111 			ps->levels[i].vddc_index = min_voltage;  in sumo_apply_state_adjust_rules()
1113 		if (ps->levels[i].sclk < min_sclk)  in sumo_apply_state_adjust_rules()
1114 			ps->levels[i].sclk =  in sumo_apply_state_adjust_rules()
1117 		ps->levels[i].ss_divider_index =  in sumo_apply_state_adjust_rules()
1118 			sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, sclk_in_sr);  in sumo_apply_state_adjust_rules()
1120 		ps->levels[i].ds_divider_index =  in sumo_apply_state_adjust_rules()
1121 			sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, SUMO_MINIMUM_ENGINE_CLOCK);  in sumo_apply_state_adjust_rules()
1123 		if (ps->levels[i].ds_divider_index > ps->levels[i].ss_divider_index + 1)  in sumo_apply_state_adjust_rules()
1124 			ps->levels[i].ds_divider_index = ps->levels[i].ss_divider_index + 1;  in sumo_apply_state_adjust_rules()
1126 		if (ps->levels[i].ss_divider_index == ps->levels[i].ds_divider_index) {  in sumo_apply_state_adjust_rules()
1127 			if (ps->levels[i].ss_divider_index > 1)  in sumo_apply_state_adjust_rules()
1128 				ps->levels[i].ss_divider_index = ps->levels[i].ss_divider_index - 1;  in sumo_apply_state_adjust_rules()
1131 		if (ps->levels[i].ss_divider_index == 0)  in sumo_apply_state_adjust_rules()
1132 			ps->levels[i].ds_divider_index = 0;  in sumo_apply_state_adjust_rules()
1134 		if (ps->levels[i].ds_divider_index == 0)  in sumo_apply_state_adjust_rules()
1135 			ps->levels[i].ss_divider_index = 0;  in sumo_apply_state_adjust_rules()
1138 			ps->levels[i].allow_gnb_slow = 1;  in sumo_apply_state_adjust_rules()
1141 			ps->levels[i].allow_gnb_slow = 0;  in sumo_apply_state_adjust_rules()
1143 			ps->levels[i].allow_gnb_slow = 0;  in sumo_apply_state_adjust_rules()
1145 			ps->levels[i].allow_gnb_slow = 1;  in sumo_apply_state_adjust_rules()
1397 	ps->levels[0] = pi->boot_pl;  in sumo_patch_boot_state()
1433 	struct sumo_pl *pl = &ps->levels[index];  in sumo_parse_pplib_clock_info()
1739 	pi->current_ps.levels[0] = pi->boot_pl;  in sumo_construct_boot_and_acpi_state()
1806 		struct sumo_pl *pl = &ps->levels[i];  in sumo_dpm_print_power_state()
1834 		pl = &ps->levels[current_index];  in sumo_dpm_debugfs_print_current_performance_level()
1858 		pl = &ps->levels[current_index];  in sumo_dpm_get_current_sclk()
1885 		pl = &ps->levels[current_index];  in sumo_dpm_get_current_vddc()
1909 		return requested_state->levels[0].sclk;  in sumo_dpm_get_sclk()
1911 		return requested_state->levels[requested_state->num_levels - 1].sclk;  in sumo_dpm_get_sclk()