| /freebsd/secure/lib/libcrypto/man/man7/ |
| H A D | migration_guide.7 | 18 .\" Set up some character translations and predefined strings. \*(-- will
24 .tr \(*W-
27 . ds -- \(*W-
29 . if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch
30 . if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch
37 . ds -- \|\(em\|
71 .\" Fear. Run. Save yourself. No user-serviceable parts.
81 . ds #H ((1u-(\\\\n(.fu%2u))*.13m)
97 . ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u"
98 . ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u'
[all …]
|
| /freebsd/crypto/openssl/doc/man7/ |
| H A D | migration_guide.pod | 5 migration_guide - OpenSSL migration guide
37 licenses|https://www.openssl.org/source/license-openssl-ssleay.txt>
39 L<Apache License v2|https://www.openssl.org/source/apache-license-2.0.txt>.
50 "high level" APIs (for example those functions prefixed with C<EVP>). They cannot
51 be accessed using the L</Low Level APIs>.
56 at configuration time using the C<enable-fips> option. If it is enabled,
74 =head3 Low Leve
[all...] |
| /freebsd/sys/contrib/device-tree/Bindings/power/supply/ |
| H A D | max17040_battery.txt | 5 - compatible : "maxim,max17040", "maxim,max17041", "maxim,max17043",
7 "maxim,max17058", "maxim,max17059" or "maxim,max77836-battery"
8 - reg: i2c slave address
11 - maxim,alert-low-soc-level : The alert threshold that sets the state of
12 charge level (%) where an interrupt is
16 - maxim,double-soc : Certain devices return double the capacity.
20 - maxim,rcomp : A value to compensate readings for various
25 - interrupts : Interrupt line see Documentation/devicetree/
26 bindings/interrupt-controller/interrupts.txt
27 - wakeup-source : This device has wakeup capabilities. Use this
[all …]
|
| H A D | maxim,max17040.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
13 - $ref: power-suppl
[all...] |
| /freebsd/sys/amd64/vmm/io/ |
| H A D | vioapic.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
64 int acnt; /* sum of pin asserts (+1) and deasserts (-1) */
68 #define VIOAPIC_LOCK(vioapic) mtx_lock_spin(&((vioapic)->mtx))
69 #define VIOAPIC_UNLOCK(vioapic) mtx_unlock_spin(&((vioapic)->mtx))
70 #define VIOAPIC_LOCKED(vioapic) mtx_owned(&((vioapic)->mtx))
75 VM_CTR1((vioapic)->vm, fmt, a1)
78 VM_CTR2((vioapic)->vm, fmt, a1, a2)
81 VM_CTR3((vioapic)->vm, fmt, a1, a2, a3)
84 VM_CTR4((vioapic)->vm, fmt, a1, a2, a3, a4)
[all …]
|
| /freebsd/sbin/conscontrol/ |
| H A D | conscontrol.8 | 1 .\"-
2 .\" SPDX-License-Identifer: BSD-2-Clause
56 There are two types of logical consoles; a high level console which
59 and a low level console.
60 The low level consol
[all...] |
| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | img,pdc-intc.txt | 10 - compatible: Specifies the compatibility list for the interrupt controller.
11 The type shall be <string> and the value shall include "img,pdc-intc".
13 - reg: Specifies the base PDC physical address(s) and size(s) of the
14 addressable register space. The type shall be <prop-encoded-array>.
16 - interrupt-controller: The presence of this property identifies the node
19 - #interrupt-cells: Specifies the number of cells needed to encode an
22 - num-perips: Number of waking peripherals.
24 - num-syswakes: Number of SysWake inputs.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
34 - <1st-cell>: The interrupt-number that identifies the interrupt source.
[all …]
|
| H A D | snps,archs-idu-intc.txt | 1 * ARC-HS Interrupt Distribution Unit
3 This optional 2nd level interrupt controller can be used in SMP configurations
9 - compatible: "snps,archs-idu-intc"
10 - interrupt-controller: This is an interrupt controller.
11 - #interrupt-cells: Must be <1> or <2>.
18 - bits[3:0] trigger type and level flags
19 1 = low-to-high edge triggered
20 2 = NOT SUPPORTED (high-to-low edge triggered)
21 4 = active high level-sensitive <<< DEFAULT
22 8 = NOT SUPPORTED (active low level-sensitive)
[all …]
|
| H A D | atmel,aic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/atmel,aic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Dharma balasubiramani <dharma.b@microchip.com>
14 The Advanced Interrupt Controller (AIC) is an 8-level priority, individually
16 hundred and twenty-eight interrupt sources.
21 - atmel,at91rm9200-aic
22 - atmel,sama5d2-aic
[all …]
|
| H A D | atmel,aic.txt | 4 - compatible: Should be:
5 - "atmel,<chip>-aic" where <chip> can be "at91rm9200", "sama5d2",
7 - "microchip,<chip>-aic" where <chip> can be "sam9x60"
9 - interrupt-controller: Identifies the node as an interrupt controller.
10 - #interrupt-cells: The number of cells to define the interrupts. It should be 3.
13 bits[3:0] trigger type and level flags:
14 1 = low-to-high edge triggered.
15 2 = high-to-low edge triggered.
16 4 = active high level-sensitive.
17 8 = active low level-sensitive.
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/watchdog/ |
| H A D | gpio-wdt.txt | 1 * GPIO-controlled Watchdog
4 - compatible: Should contain "linux,wdt-gpio".
5 - gpios: From common gpio binding; gpio connection to WDT reset pin.
6 - hw_algo: The algorithm used by the driver. Should be one of the
8 - toggle: Either a high-to-low or a low-to-high transition clears
10 left floating or connected to a three-state buffer.
11 - level: Low or high level starts counting WDT timeout,
12 the opposite level disables the WDT. Active level is determined
14 - hw_margin_ms: Maximum time to reset watchdog circuit (milliseconds).
17 - always-running: If the watchdog timer cannot be disabled, add this flag to
[all …]
|
| H A D | gpio-wdt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/gpio-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Robert Marko <robert.marko@sartura.hr>
14 const: linux,wdt-gpio
24 - description:
25 Either a high-to-low or a low-to-high transition clears the WDT counter.
27 to a three-state buffer.
29 - description:
[all …]
|
| H A D | linux,wdt-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/linux,wdt-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO-controlled Watchdog
10 - Guenter Roeck <linux@roeck-us.net>
11 - Robert Marko <robert.marko@sartura.hr>
15 const: linux,wdt-gpio
24 - description:
25 Either a high-to-low or a low-to-high transition clears the WDT counter.
[all …]
|
| /freebsd/share/man/man4/ |
| H A D | mac_mls.4 | 1 .\" Copyright (c) 2002-2004 Networks Associates Technology, Inc.
7 .\" DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the
36 .Nd "Multi-Level Security confidentiality policy"
40 .Bd -ragged -offset indent
47 .Bd -ragged -offset indent
53 .Bd -literal -offset indent
59 policy module implements the Multi-Level Security, or MLS model,
63 each subject's MLS label contains information on its clearance level,
67 made up of a sensitivity level and zero or more compartments.
71 The sensitivity level is expressed as a value between 0 and
[all …]
|
| H A D | mac_biba.4 | 1 .\" Copyright (c) 2002-2004 Networks Associates Technology, Inc.
7 .\" DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the
40 .Bd -ragged -offset indent
47 .Bd -ragged -offset indent
53 .Bd -literal -offset indent
63 up of hierarchal grades, and non-hierarchal components.
69 The non-hierarchal compartment field is expressed as a set of up to 256
71 A complete label consists of both hierarchal and non-hierarchal elements.
74 .Bl -column -offset indent ".Li biba/equal" "lower than all other labels"
76 .It Li biba/low Ta "lower than all other labels"
[all …]
|
| H A D | uart.4 | 1 .\"-
2 .\" SPDX-License-Identifier: BSD-2-Clause
53 .Bl -tag -compact -width 0x000000
59 set RX FIFO trigger level to ``low'' (NS8250 only)
61 set RX FIFO trigger level to ``medium low'' (NS8250 only)
63 set RX FIFO trigger level to ``medium high'' (default, NS8250 only)
65 set RX FIFO trigger level to ``high'' (NS8250 only)
72 EIA RS-232C (CCITT V.24) serial communications interface.
112 It contains the bus attachments and the low-level interrupt handler.
144 .Bl -bullet -compact
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/dma/stm32/ |
| H A D | st,stm32-dma3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 It is either called LPDMA (Low Power), GPDMA (General Purpose) or HPDMA (High
22 described in "#dma-cells" property description below, using a three-cell
26 - Amelie Delaunay <amelie.delaunay@foss.st.com>
29 - $ref: /schemas/dma/dma-controller.yaml#
33 const: st,stm32mp25-dma3
42 Should contain all of the per-channel DMA interrupts in ascending order
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/thermal/ |
| H A D | nvidia,tegra124-soctherm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/thermal/nvidia,tegra124-soctherm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 polled or interrupt-based thermal monitoring, CPU and GPU throttling based
21 - nvidia,tegra124-soctherm
22 - nvidia,tegra132-soctherm
23 - nvidia,tegra210-soctherm
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | gpio-nmk.txt | 4 - compatible : Should be "st,nomadik-gpio".
5 - reg : Physical base address and length of the controller's registers.
6 - interrupts : The interrupt outputs from the controller.
7 - #gpio-cells : Should be two:
10 - bits[3:0] trigger type and level flags:
11 1 = low-to-high edge triggered.
12 2 = high-to-low edge triggered.
13 4 = active high level-sensitive.
14 8 = active low level-sensitive.
15 - gpio-controller : Marks the device node as a GPIO controller.
[all …]
|
| H A D | gpio-vf610.txt | 8 - compatible : Should be "fsl,<soc>-gpio", below is supported list:
9 "fsl,vf610-gpio"
10 "fsl,imx7ulp-gpio"
11 - reg : The first reg tuple represents the PORT module, the second tuple
13 - interrupts : Should be the port interrupt shared by all 32 pins.
14 - gpio-controller : Marks the device node as a gpio controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and
18 1 = active low
19 - interrupt-controller: Marks the device node as an interrupt controller.
20 - #interrupt-cells : Should be 2. The first cell is the GPIO number.
[all …]
|
| H A D | nvidia,tegra20-gpio.txt | 4 - compatible : "nvidia,tegra<chip>-gpio"
5 - reg : Physical base address and length of the controller's registers.
6 - interrupts : The interrupt outputs from the controller. For Tegra20,
9 - #gpio-cells : Should be two. The first cell is the pin number and the
11 - bit 0 specifies polarity (0 for normal, 1 for inverted)
12 - gpio-controller : Marks the device node as a GPIO controller.
13 - #interrupt-cells : Should be 2.
16 bits[3:0] trigger type and level flags:
17 1 = low-to-high edge triggered.
18 2 = high-to-low edge triggered.
[all …]
|
| H A D | gpio-zynq.txt | 2 -------------------------------------------
5 - #gpio-cells : Should be two
6 - First cell is the GPIO line number
7 - Second cell is used to specify optional
9 - compatible : Should be "xlnx,zynq-gpio-1.0" or
10 "xlnx,zynqmp-gpio-1.0" or "xlnx,versal-gpio-1.0
11 or "xlnx,pmc-gpio-1.0
12 - clocks : Clock specifier (see clock bindings for details)
13 - gpio-controller : Marks the device node as a GPIO controller.
14 - interrupts : Interrupt specifier (see interrupt bindings for
[all …]
|
| H A D | nvidia,tegra20-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra20-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra GPIO Controller (Tegra20 - Tegra210)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-gpio
18 - nvidia,tegra30-gpio
[all …]
|
| H A D | brcm,brcmstb-gpio.txt | 3 The controller's registers are organized as sets of eight 32-bit
9 - compatible:
10 Must be "brcm,brcmstb-gpio"
12 - reg:
16 - #gpio-cells:
19 bit[0]: polarity (0 for active-high, 1 for active-low)
21 - gpio-controller:
24 - brcm,gpio-bank-widths:
30 - interrupts:
33 - interrupts-extended:
[all …]
|
| H A D | gpio-omap.txt | 4 - compatible:
5 - "ti,omap2-gpio" for OMAP2 controllers
6 - "ti,omap3-gpio" for OMAP3 controllers
7 - "ti,omap4-gpio" for OMAP4 controllers
8 - reg : Physical base address of the controller and length of memory mapped
10 - gpio-controller : Marks the device node as a GPIO controller.
11 - #gpio-cells : Should be two.
12 - first cell is the pin number
13 - second cell is used to specify optional parameters (unused)
14 - interrupt-controller: Mark the device node as an interrupt controller.
[all …]
|