| /freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a65/ |
| H A D | cache.json | 111 …iption": "Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetc…
114 …iption": "Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetc…
117 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
120 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
123 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
126 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
141 …"PublicDescription": "Level 2 cache write streaming mode. This event counts for each cycle where t…
144 …"BriefDescription": "Level 2 cache write streaming mode. This event counts for each cycle where th…
147 …"PublicDescription": "Level 3 cache write streaming mode. This event counts for each cycle where t…
150 …"BriefDescription": "Level 3 cache write streaming mode. This event counts for each cycle where th…
[all …]
|
| /freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a55/ |
| H A D | cache.json | 105 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
108 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
111 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
114 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
117 …ption": "Level 1 data cache refill due to prefetch. This event counts any linefills from the prefe…
120 …ption": "Level 1 data cache refill due to prefetch. This event counts any linefills from the prefe…
123 …"PublicDescription": "Level 2 cache write streaming mode. This event counts for each cycle where t…
126 …"BriefDescription": "Level 2 cache write streaming mode. This event counts for each cycle where th…
129 …"PublicDescription": "Level 1 data cache entering write streaming mode.This event counts for each …
132 …"BriefDescription": "Level 1 data cache entering write streaming mode.This event counts for each e…
[all …]
|
| /freebsd/sys/contrib/zstd/lib/compress/ |
| H A D | clevels.h | 5 * This source code is licensed under both the BSD-style license (found in the
8 * You may select, at your option, one of the above-listed licenses.
17 /*-===== Pre-defined compression levels =====-*/
26 { /* "default" - for any srcSize > 256 KB */
29 { 19, 13, 14, 1, 7, 0, ZSTD_fast }, /* level 1 */
30 { 20, 15, 16, 1, 6, 0, ZSTD_fast }, /* level 2 */
31 { 21, 16, 17, 1, 5, 0, ZSTD_dfast }, /* level 3 */
32 { 21, 18, 18, 1, 5, 0, ZSTD_dfast }, /* level 4 */
33 { 21, 18, 19, 3, 5, 2, ZSTD_greedy }, /* level 5 */
34 { 21, 18, 19, 3, 5, 4, ZSTD_lazy }, /* level 6 */
[all …]
|
| /freebsd/lib/libpmc/pmu-events/arch/s390/cf_z14/ |
| H A D | extended.json | 5 "BriefDescription": "L1D Read-only Exclusive Writes",
6 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
12 …"PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2…
18 …e data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on thi…
23 "BriefDescription": "DTLB2 One-Megabyte Page Writes",
24 …en into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte pa…
29 "BriefDescription": "DTLB2 Two-Gigabyte Page Writes",
30 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB"
36 …tion": "A directory write to the Level-1 Data cache directory where the returned cache line was so…
42 …"A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the reque…
[all …]
|
| /freebsd/lib/libpmc/pmu-events/arch/s390/cf_z196/ |
| H A D | extended.json | 6 …ption": "A directory write to the Level-1 D-Cache directory where the returned cache line was sour…
12 …ption": "A directory write to the Level-1 I-Cache directory where the returned cache line was sour…
18 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
24 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
30 "PublicDescription": "Incremented by one for every store sent to Level-2 cache"
35 "BriefDescription": "L1D Off-Book L3 Sourced Writes",
36 …on": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced…
41 "BriefDescription": "L1D On-Book L4 Sourced Writes",
42 …on": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced…
47 "BriefDescription": "L1I On-Book L4 Sourced Writes",
[all …]
|
| /freebsd/lib/libpmc/pmu-events/arch/arm64/ |
| H A D | common-and-microarch.json | 9 "PublicDescription": "Level 1 instruction cache refill",
12 "BriefDescription": "Level 1 instruction cache refill"
15 "PublicDescription": "Attributable Level 1 instruction TLB refill",
18 "BriefDescription": "Attributable Level 1 instruction TLB refill"
21 "PublicDescription": "Level 1 data cache refill",
24 "BriefDescription": "Level 1 data cache refill"
27 "PublicDescription": "Level 1 data cache access",
30 "BriefDescription": "Level 1 data cache access"
33 "PublicDescription": "Attributable Level 1 data TLB refill",
36 "BriefDescription": "Attributable Level 1 data TLB refill"
[all …]
|
| H A D | recommended.json | 3 "PublicDescription": "Attributable Level 1 data cache access, read",
9 "PublicDescription": "Attributable Level 1 data cache access, write",
15 "PublicDescription": "Attributable Level 1 data cache refill, read",
21 "PublicDescription": "Attributable Level 1 data cache refill, write",
27 "PublicDescription": "Attributable Level 1 data cache refill, inner",
33 "PublicDescription": "Attributable Level 1 data cache refill, outer",
39 "PublicDescription": "Attributable Level 1 data cache Write-Back, victim",
42 "BriefDescription": "L1D cache Write-Back, victim"
45 "PublicDescription": "Level 1 data cache Write-Back, cleaning and coherency",
48 "BriefDescription": "L1D cache Write-Back, cleaning and coherency"
[all …]
|
| H A D | armv8-recommended.json | 3 "PublicDescription": "Attributable Level 1 data cache access, read",
9 "PublicDescription": "Attributable Level 1 data cache access, write",
15 "PublicDescription": "Attributable Level 1 data cache refill, read",
21 "PublicDescription": "Attributable Level 1 data cache refill, write",
27 "PublicDescription": "Attributable Level 1 data cache refill, inner",
33 "PublicDescription": "Attributable Level 1 data cache refill, outer",
39 "PublicDescription": "Attributable Level 1 data cache Write-Back, victim",
42 "BriefDescription": "L1D cache Write-Back, victim"
45 "PublicDescription": "Level 1 data cache Write-Back, cleaning and coherency",
48 "BriefDescription": "L1D cache Write-Back, cleaning and coherency"
[all …]
|
| /freebsd/lib/libpmc/pmu-events/arch/s390/cf_zec12/ |
| H A D | extended.json | 6 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
12 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
18 …tion": "A directory write to the Level-1 Data cache directory where the returned cache line was so…
24 …": "A directory write to the Level-1 Instruction cache directory where the returned cache line was…
30 …tion": "A directory write to the Level-1 Data cache directory where the returned cache line was so…
36 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
42 …"PublicDescription": "A directory write to the Level-1 Data cache where the installed cache line w…
48 …"PublicDescription": "A directory write to the Level-1 Instruction cache where the installed cache…
53 "BriefDescription": "L1D Read-only Exclusive Writes",
54 …"PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a …
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/cpufreq/ |
| H A D | cpufreq-qcom-hw.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
21 - description: v1 of CPUFREQ HW
23 - enum:
24 - qcom,qcm2290-cpufreq-hw
25 - qcom,sc7180-cpufreq-hw
26 - qcom,sdm670-cpufreq-hw
[all …]
|
| /freebsd/lib/libpmc/pmu-events/arch/s390/cf_z10/ |
| H A D | extended.json | 6 …ption": "A directory write to the Level-1 I-Cache directory where the returned cache line was sour…
12 …ption": "A directory write to the Level-1 D-Cache directory where the installed cache line was sou…
18 …ption": "A directory write to the Level-1 I-Cache directory where the installed cache line was sou…
24 …ption": "A directory write to the Level-1 D-Cache directory where the installtion cache line was s…
30 …iption": "A directory write to the Level-1 I-Cache directory where the installed cache line was so…
36 …iption": "A directory write to the Level-1 D-Cache directory where the installed cache line was so…
42 …"PublicDescription": "A directory write to the Level-1 D-Cache directory where the installed cache…
48 …"PublicDescription": "A directory write to the Level-1 I-Cache where the installed cache line was …
53 "BriefDescription": "L1D Read-only Exclusive Writes",
54 …"PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a …
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/opp/ |
| H A D | opp-v2-qcom-level.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-qcom-level.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Niklas Cassel <nks@flawful.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2-qcom-level
20 '^opp-?[0-9]+$':
25 opp-level: true
27 qcom,opp-fuse-level:
[all …]
|
| /freebsd/sys/contrib/device-tree/src/arm64/rockchip/ |
| H A D | rockchip-pinconf.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /omit-if-no-ref/
8 pcfg_pull_up: pcfg-pull-up {
9 bias-pull-up;
12 /omit-if-no-ref/
13 pcfg_pull_down: pcfg-pull-down {
14 bias-pull-down;
17 /omit-if-no-ref/
18 pcfg_pull_none: pcfg-pull-none {
19 bias-disable;
[all …]
|
| /freebsd/lib/libc/gen/ |
| H A D | sysctl.3 | 9 .\" 2. Redistributions in binary form must reproduce the above copyright
157 .Bd -literal -offset indent -compact
170 if (sysctl(mib, 4, &kp, &len, NULL, 0) == -1)
177 The top level names are defined with a CTL_ prefix in
182 .Bl -column CTLXMACHDEPXXX "Next Level NamesXXXXXX" -offset indent
183 .It Sy Name Ta Sy Next Level Names Ta Sy Description
190 .It Dv CTL_USER Ta In sys/sysctl.h Ta User-level
197 .Bd -literal -offset indent -compact
198 int mib[2], maxproc;
204 sysctl(mib, 2, &maxproc, &len, NULL, 0);
[all …]
|
| /freebsd/sys/contrib/device-tree/src/arm64/amd/ |
| H A D | elba-16core.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Copyright 2020-2023 Advanced Micro Devices, Inc.
8 #address-cells = <1>;
9 #size-cells = <0>;
11 cpu-map {
44 compatible = "arm,cortex-a72";
46 next-level-cache = <&l2_0>;
47 enable-method = "psci";
52 compatible = "arm,cortex-a72";
54 next-level-cache = <&l2_0>;
[all …]
|
| /freebsd/sys/contrib/device-tree/src/arm64/apple/ |
| H A D | t600x-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 * Other names: H13J, "Jade Chop", "Jade", "Jade 2C"
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
18 cpu-map {
63 enable-method = "spin-table";
64 cpu-release-addr = <0 0>; /* To be filled by loader */
65 next-level-cache = <&l2_cache_0>;
[all …]
|
| /freebsd/secure/lib/libcrypto/man/man3/ |
| H A D | SSL_CTX_set_security_level.3 | 18 .\" Set up some character translations and predefined strings. \*(-- will
24 .tr \(*W-
27 . ds -- \(*W-
29 . if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch
30 . if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch
37 . ds -- \|\(em\|
62 . tm Index:\\$1\t\\n%\t"\\$2"
64 . if !\nF==2 \{\
66 . nr F 2
71 .\" Fear. Run. Save yourself. No user-serviceable parts.
[all …]
|
| /freebsd/lib/libpmc/pmu-events/arch/s390/cf_z13/ |
| H A D | extended.json | 5 "BriefDescription": "L1D Read-only Exclusive Writes",
6 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
12 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
18 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
23 "BriefDescription": "DTLB1 One-Megabyte Page Writes",
24 …on": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a …
29 "BriefDescription": "DTLB1 Two-Gigabyte Page Writes",
30 …on": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a …
36 …tion": "A directory write to the Level-1 Data cache directory where the returned cache line was so…
42 …"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation …
[all …]
|
| /freebsd/tools/tools/usbtest/ |
| H A D | usbtest.c | 1 /*-
2 * Copyright (c) 2010-2022 Hans Petter Selasky
9 * 2. Redistributions in binary form must reproduce the above copyright
71 noise_rem /= 2; in usb_ts_rand_noise()
79 temp |= (-0x800000); in usb_ts_rand_noise()
85 usb_ts_show_menu(uint8_t level, const char *title, const char *fmt,...) in usb_ts_show_menu() argument
100 for (x = 0; x != level; x++) { in usb_ts_show_menu()
101 if ((x + 1) == level) in usb_ts_show_menu()
107 printf("] - %s:\n\n", title); in usb_ts_show_menu()
112 printf("%s", indent[level]); in usb_ts_show_menu()
[all …]
|
| /freebsd/share/man/man4/ |
| H A D | psm.4 | 3 .\" Kazutaka YOKOTA <yokota@zodiac.mech.utsunomiya-u.ac.jp>
12 .\" 2. Redistributions in binary form must reproduce the above copyright
27 .Dd June 2, 2020
32 .Nd PS/2 mouse style pointing device driver
47 driver provides support for the PS/2 mouse style pointing device.
51 As the PS/2 mouse port is located
60 Basic PS/2 style pointing device has two or three buttons.
63 The PS/2 style pointing device usually has several grades of resolution,
76 .Xr ioctl 2
84 The PS/2 style pointing device typically supports 10, 20, 40, 60, 80, 100
[all …]
|
| /freebsd/stand/ficl/softwords/ |
| H A D | ifbrack.fr | 8 : ?[if] ( c-addr u -- c-addr u flag )
9 2dup s" [if]" compare-insensitive 0=
12 : ?[else] ( c-addr u -- c-addr u flag )
13 2dup s" [else]" compare-insensitive 0=
16 : ?[then] ( c-addr u -- c-addr u flag )
17 2dup s" [then]" compare-insensitive 0= >r
18 2dup s" [endif]" compare-insensitive 0= r>
22 set-current
24 : [else] ( -- )
25 1 \ ( level )
[all …]
|
| /freebsd/sys/contrib/device-tree/src/arm64/hisilicon/ |
| H A D | hip05.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip05-d02";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
|
| /freebsd/lib/libpmc/pmu-events/arch/arm64/ampere/emag/ |
| H A D | cache.json | 78 …"PublicDescription": "Level 2 access to data TLB that caused a page table walk. This event counts …
84 …"PublicDescription": "Level 2 access to instruciton TLB that caused a page table walk. This event …
108 "PublicDescription": "Level 1 data cache late miss",
114 "PublicDescription": "Level 1 data cache prefetch request",
120 "PublicDescription": "Level 2 data cache prefetch request",
126 "PublicDescription": "Level 1 stage 2 TLB refill",
129 "BriefDescription": "L1 stage 2 TLB refill"
132 "PublicDescription": "Page walk cache level-0 stage-1 hit",
135 "BriefDescription": "Page walk, L0 stage-1 hit"
138 "PublicDescription": "Page walk cache level-1 stage-1 hit",
[all …]
|
| /freebsd/contrib/ofed/infiniband-diags/man/ |
| H A D | smpdump.8 | 5 SMPDUMP \-
7 .nr rst2man-indent-level 0
10 \\$1 \\n[an-margin]
11 level \\n[rst2man-indent-level]
12 level margin: \\n[rst2man-indent\\n[rst2man-indent-level]]
13 -
14 \\n[rst2man-indent0]
15 \\n[rst2man-indent1]
16 \\n[rst2man-indent2]
21 . nr rst2man-indent\\n[rst2man-indent-level] \\n[an-margin]
[all …]
|
| /freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a75/ |
| H A D | cache.json | 111 "PublicDescription": "Number of ways read in the instruction cache - Tag RAM",
114 "BriefDescription": "Number of ways read in the instruction cache - Tag RAM"
117 "PublicDescription": "Number of ways read in the instruction cache - Data RAM",
120 "BriefDescription": "Number of ways read in the instruction cache - Data RAM"
129 "PublicDescription": "Level 1 PLD TLB refill",
132 "BriefDescription": "Level 1 PLD TLB refill"
135 …ublicDescription": "Level 2 preload and MMU prefetcher TLB access. This event only counts software…
138 …BriefDescription": "Level 2 preload and MMU prefetcher TLB access. This event only counts software…
141 "PublicDescription": "Level 1 TLB flush",
144 "BriefDescription": "Level 1 TLB flush"
[all …]
|