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/linux/security/landlock/
H A Druleset.c87 * LANDLOCK_MAX_NUM_LAYERS layers. in build_check_rule()
111 const struct landlock_layer (*const layers)[], const u32 num_layers, in create_rule() argument
126 new_rule = kzalloc_flex(*new_rule, layers, new_num_layers, in create_rule()
140 memcpy(new_rule->layers, layers, in create_rule()
141 flex_array_size(new_rule, layers, num_layers)); in create_rule()
144 new_rule->layers[new_rule->num_layers - 1] = *new_layer; in create_rule()
194 * @layers: One or multiple layers to be copied into the new rule.
195 * @num_layers: The number of @layers entries.
197 * When user space requests to add a new rule to a ruleset, @layers only
202 * When merging a ruleset in a domain, or copying a domain, @layers will be
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H A Druleset.h103 * @num_layers: Number of entries in @layers.
107 * @layers: Stack of layers, from the latest to the newest, implemented
110 struct landlock_layer layers[] __counted_by(num_layers);
169 * @num_layers: Number of layers that are used in this
170 * ruleset. This enables to check that all the layers
178 * A domain saves all layers of merged rulesets in a
180 * last one. These layers are used when merging
184 * layers are set once and never changed for the
/linux/Documentation/devicetree/bindings/display/
H A Dxylon,logicvc-display.yaml14 The Xylon LogiCVC is a display controller that supports multiple layers.
24 Layers are declared in the "layers" sub-node and have dedicated configuration.
109 xylon,layers-configurable:
112 Configuration of layers' size, position and offset is enabled
115 layers:
187 The description of the display controller layers, containing layer
207 - layers
238 xylon,layers-configurable;
240 layers {
/linux/drivers/edac/
H A Dpasemi_edac.c183 struct edac_mc_layer layers[2]; in pasemi_edac_probe() local
200 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in pasemi_edac_probe()
201 layers[0].size = PASEMI_EDAC_NR_CSROWS; in pasemi_edac_probe()
202 layers[0].is_virt_csrow = true; in pasemi_edac_probe()
203 layers[1].type = EDAC_MC_LAYER_CHANNEL; in pasemi_edac_probe()
204 layers[1].size = PASEMI_EDAC_NR_CHANS; in pasemi_edac_probe()
205 layers[1].is_virt_csrow = false; in pasemi_edac_probe()
206 mci = edac_mc_alloc(system_mmc_id++, ARRAY_SIZE(layers), layers, in pasemi_edac_probe()
H A Dhighbank_mc_edac.c149 struct edac_mc_layer layers[2]; in highbank_mc_probe() local
163 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in highbank_mc_probe()
164 layers[0].size = 1; in highbank_mc_probe()
165 layers[0].is_virt_csrow = true; in highbank_mc_probe()
166 layers[1].type = EDAC_MC_LAYER_CHANNEL; in highbank_mc_probe()
167 layers[1].size = 1; in highbank_mc_probe()
168 layers[1].is_virt_csrow = false; in highbank_mc_probe()
169 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, in highbank_mc_probe()
H A Di82860_edac.c187 struct edac_mc_layer layers[2]; in i82860_probe1() local
200 layers[0].type = EDAC_MC_LAYER_CHANNEL; in i82860_probe1()
201 layers[0].size = 2; in i82860_probe1()
202 layers[0].is_virt_csrow = true; in i82860_probe1()
203 layers[1].type = EDAC_MC_LAYER_SLOT; in i82860_probe1()
204 layers[1].size = 8; in i82860_probe1()
205 layers[1].is_virt_csrow = true; in i82860_probe1()
206 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in i82860_probe1()
H A Damd76x_edac.c237 struct edac_mc_layer layers[2]; in amd76x_probe1() local
246 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in amd76x_probe1()
247 layers[0].size = AMD76X_NR_CSROWS; in amd76x_probe1()
248 layers[0].is_virt_csrow = true; in amd76x_probe1()
249 layers[1].type = EDAC_MC_LAYER_CHANNEL; in amd76x_probe1()
250 layers[1].size = 1; in amd76x_probe1()
251 layers[1].is_virt_csrow = false; in amd76x_probe1()
252 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in amd76x_probe1()
H A Daspeed_edac.c282 struct edac_mc_layer layers[2]; in aspeed_probe() local
307 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in aspeed_probe()
308 layers[0].size = 1; in aspeed_probe()
309 layers[0].is_virt_csrow = true; in aspeed_probe()
310 layers[1].type = EDAC_MC_LAYER_CHANNEL; in aspeed_probe()
311 layers[1].size = 1; in aspeed_probe()
312 layers[1].is_virt_csrow = false; in aspeed_probe()
314 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in aspeed_probe()
H A Docteon_edac-lmc.c228 struct edac_mc_layer layers[1]; in octeon_lmc_edac_probe() local
233 layers[0].type = EDAC_MC_LAYER_CHANNEL; in octeon_lmc_edac_probe()
234 layers[0].size = 1; in octeon_lmc_edac_probe()
235 layers[0].is_virt_csrow = false; in octeon_lmc_edac_probe()
246 mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, sizeof(struct octeon_lmc_pvt)); in octeon_lmc_edac_probe()
278 mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, sizeof(struct octeon_lmc_pvt)); in octeon_lmc_edac_probe()
H A Dedac_mc.c70 edac_layer_name[mci->layers[i].type], in edac_dimm_info_location()
206 kfree(mci->layers); in mci_release()
295 edac_layer_name[mci->layers[layer].type], in edac_mc_alloc_dimms()
308 if (mci->layers[0].is_virt_csrow) { in edac_mc_alloc_dimms()
325 if (pos[layer] < mci->layers[layer].size) in edac_mc_alloc_dimms()
336 struct edac_mc_layer *layers, in edac_mc_alloc() argument
353 tot_dimms *= layers[idx].size; in edac_mc_alloc()
355 if (layers[idx].is_virt_csrow) in edac_mc_alloc()
356 tot_csrows *= layers[idx].size; in edac_mc_alloc()
358 tot_channels *= layers[idx].size; in edac_mc_alloc()
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H A Dx38_edac.c322 struct edac_mc_layer layers[2]; in x38_probe1() local
338 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in x38_probe1()
339 layers[0].size = X38_RANKS; in x38_probe1()
340 layers[0].is_virt_csrow = true; in x38_probe1()
341 layers[1].type = EDAC_MC_LAYER_CHANNEL; in x38_probe1()
342 layers[1].size = x38_channel_num; in x38_probe1()
343 layers[1].is_virt_csrow = false; in x38_probe1()
347 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in x38_probe1()
H A Di3200_edac.c340 struct edac_mc_layer layers[2]; in i3200_probe1() local
355 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in i3200_probe1()
356 layers[0].size = I3200_DIMMS; in i3200_probe1()
357 layers[0].is_virt_csrow = true; in i3200_probe1()
358 layers[1].type = EDAC_MC_LAYER_CHANNEL; in i3200_probe1()
359 layers[1].size = nr_channels; in i3200_probe1()
360 layers[1].is_virt_csrow = false; in i3200_probe1()
363 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(struct i3200_priv)); in i3200_probe1()
H A Di3000_edac.c313 struct edac_mc_layer layers[2]; in i3000_probe1() local
356 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in i3000_probe1()
357 layers[0].size = I3000_RANKS / nr_channels; in i3000_probe1()
358 layers[0].is_virt_csrow = true; in i3000_probe1()
359 layers[1].type = EDAC_MC_LAYER_CHANNEL; in i3000_probe1()
360 layers[1].size = nr_channels; in i3000_probe1()
361 layers[1].is_virt_csrow = false; in i3000_probe1()
362 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in i3000_probe1()
H A Di82875p_edac.c391 struct edac_mc_layer layers[2]; in i82875p_probe1() local
406 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in i82875p_probe1()
407 layers[0].size = I82875P_NR_CSROWS(nr_chans); in i82875p_probe1()
408 layers[0].is_virt_csrow = true; in i82875p_probe1()
409 layers[1].type = EDAC_MC_LAYER_CHANNEL; in i82875p_probe1()
410 layers[1].size = nr_chans; in i82875p_probe1()
411 layers[1].is_virt_csrow = false; in i82875p_probe1()
412 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); in i82875p_probe1()
H A De7xxx_edac.c424 struct edac_mc_layer layers[2]; in e7xxx_probe1() local
443 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in e7xxx_probe1()
444 layers[0].size = E7XXX_NR_CSROWS; in e7xxx_probe1()
445 layers[0].is_virt_csrow = true; in e7xxx_probe1()
446 layers[1].type = EDAC_MC_LAYER_CHANNEL; in e7xxx_probe1()
447 layers[1].size = drc_chan + 1; in e7xxx_probe1()
448 layers[1].is_virt_csrow = false; in e7xxx_probe1()
449 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); in e7xxx_probe1()
H A Dal_mc_edac.c219 struct edac_mc_layer layers[1]; in al_mc_edac_probe() local
233 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in al_mc_edac_probe()
234 layers[0].size = 1; in al_mc_edac_probe()
235 layers[0].is_virt_csrow = false; in al_mc_edac_probe()
236 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, in al_mc_edac_probe()
/linux/drivers/media/dvb-frontends/
H A Dtc90522.c201 int layers; in tc90522s_get_frontend() local
209 layers = 0; in tc90522s_get_frontend()
236 layers = (v > 0) ? 2 : 1; in tc90522s_get_frontend()
284 stats->len = layers; in tc90522s_get_frontend()
287 for (i = 0; i < layers; i++) in tc90522s_get_frontend()
290 for (i = 0; i < layers; i++) { in tc90522s_get_frontend()
298 stats->len = layers; in tc90522s_get_frontend()
300 for (i = 0; i < layers; i++) in tc90522s_get_frontend()
303 for (i = 0; i < layers; i++) { in tc90522s_get_frontend()
336 int layers; in tc90522t_get_frontend() local
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/linux/fs/overlayfs/
H A Dsuper.c425 * file handles, so they require that all layers support them. in ovl_lower_dir()
514 pr_err("upper fs is r/o, try multi-lower layers mount\n"); in ovl_get_upper()
938 * as all lower layers with null uuid are on the same fs. in ovl_lower_uuid_ok()
999 * The fsid after the last lower fsid is used for the data layers.
1028 struct ovl_fs_context *ctx, struct ovl_layer *layers) in ovl_get_layers() argument
1040 * and the last fsid is reserved for "null fs" of the data layers. in ovl_get_layers()
1045 * All lower layers that share the same fs as upper layer, use the same in ovl_get_layers()
1082 * Check if lower root conflicts with this overlay layers before in ovl_get_layers()
1109 * Make lower layers R/O. That way fchmod/fchown on lower file in ovl_get_layers()
1114 layers[ofs->numlayer].trap = trap; in ovl_get_layers()
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H A Dovl_entry.h60 /* Number of unique fs among layers including upper fs */
62 /* Number of data-only lower layers */
64 struct ovl_layer *layers; member
97 /* Number of lower layers, not including data-only layers */
105 return ofs->layers[0].mnt; in ovl_upper_mnt()
H A Dparams.c208 /* count layers, not colons */ in ovl_parse_param_split_lowerdirs()
317 return invalfc(fc, "regular lower layers cannot follow data layers"); in ovl_mount_dir_check()
497 * Set "/lower1", "/lower2", and "/lower3" as lower layers and
498 * "/data1" and "/data2" as data lower layers. Any existing lower
499 * layers are replaced.
514 /* drop all existing lower layers */ in ovl_parse_param_lowerdir()
568 * there are no data layers. in ovl_parse_param_lowerdir()
571 pr_err("regular lower layers cannot follow data lower layers\n"); in ovl_parse_param_lowerdir()
785 * By default we allocate for three lower layers. It's likely in ovl_init_fs_context()
835 iput(ofs->layers[i].trap); in ovl_free_fs()
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/linux/Documentation/scsi/
H A Dscsi_eh.rst152 Note that this does not mean lower layers are quiescent. If a LLDD
153 completed a scmd with error status, the LLDD and lower layers are
155 has timed out, unless hostt->eh_timed_out() made lower layers forget
157 active as long as lower layers are concerned and completion could
206 lower layers and lower layers are ready to process or fail the scmd
364 that lower layers have forgotten about the scmd and we can
373 and STU doesn't make lower layers forget about those
375 if STU succeeds leaving lower layers in an inconsistent
428 On completion, the handler should have made lower layers forget about
468 - Know that timed out scmds are still active on lower layers. Make
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/linux/drivers/staging/most/Documentation/
H A Ddriver_usage.txt8 MOST defines the protocol, hardware and software layers necessary to allow
19 consumer devices via optical or electrical physical layers directly to one
27 three layers. From bottom up these layers are: the adapter layer, the core
31 routing through all three layers, the configuration of the driver, the
35 For each of the other two layers a set of modules is provided. Those can be
/linux/include/net/caif/
H A Dcaif_layer.h127 * It defines CAIF layering structure, used by all CAIF Layers and the
128 * layers interfacing CAIF.
134 * Principles for layering of protocol layers:
135 * - All layers must use this structure. If embedding it, then place this
167 * - If parsing succeeds (and above layers return OK) then
251 * logical CAIF connection. Used by service layers to
/linux/Documentation/driver-api/fpga/
H A Dintro.rst9 * The FPGA subsystem separates upper layers (userspace interfaces and
10 enumeration) from lower layers that know how to program a specific
13 * Code should not be shared between upper and lower layers. This
/linux/drivers/gpu/drm/xlnx/
H A Dzynqmp_dpsub.h60 * @layers: Video and graphics layers
81 struct zynqmp_disp_layer *layers[ZYNQMP_DPSUB_NUM_LAYERS]; member

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