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/linux/Documentation/devicetree/bindings/display/
H A Dxylon,logicvc-display.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
20 synthesis time. As a result, many of the device-tree bindings are meant to
24 Layers are declared in the "layers" sub-node and have dedicated configuration.
25 In version 3 of the controller, each layer has fixed memory offset and address
32 - xylon,logicvc-3.02.a-display
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/linux/drivers/gpu/drm/atmel-hlcdc/
H A Datmel_hlcdc_plane.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
10 #include <linux/mfd/atmel-hlcdc.h>
24 * struct atmel_hlcdc_plane_state - Atmel HLCDC Plane state structure.
190 return -ENOTSUPP; in atmel_hlcdc_format_to_plane_mode()
265 factor = (256 * ((8 * (srcsize - 1)) - phide in atmel_hlcdc_plane_phiscaler_get_factor()
629 struct atmel_hlcdc_plane *primary; atmel_hlcdc_plane_prepare_disc_area() local
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/linux/drivers/gpu/drm/xlnx/
H A Dzynqmp_kms.c1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP DisplayPort Subsystem - KMS API
5 * Copyright (C) 2017 - 2021 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
48 return container_of(drm, struct zynqmp_dpsub_drm, dev)->dpsub; in to_zynqmp_dpsub()
51 /* --
81 struct zynqmp_disp_layer *layer = dpsub->layers[plane->index]; zynqmp_dpsub_plane_atomic_disable() local
99 struct zynqmp_disp_layer *layer = dpsub->layers[plane->index]; zynqmp_dpsub_plane_atomic_update() local
154 struct zynqmp_disp_layer *layer = dpsub->layers[i]; zynqmp_dpsub_create_planes() local
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/linux/drivers/ata/
H A Dpata_jmicron.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_jmicron.c - JMicron ATA driver for non AHCI mode. This drives the
31 * jmicron_pre_reset - check for 40/80 pin
38 * either as primary or secondary (or neither). We don't do any policy
44 struct ata_port *ap = link->ap; in jmicron_pre_reset()
45 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in jmicron_pre_reset()
48 int port_mask = 1<< (4 * ap->port_no); in jmicron_pre_reset()
49 int port = ap->port_no; in jmicron_pre_reset()
55 return -ENOENT; in jmicron_pre_reset()
69 as the internal primary channel */ in jmicron_pre_reset()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
10 uses pata-platform driver to enable the relevant driver in the
21 If you want to use an ATA hard disk, ATA tape drive, ATA CD-ROM or
62 <file:Documentation/admin-guide/kernel-parameters.txt>.
76 This option adds support for ATA-related ACPI objects.
107 comment "Controllers with non-SFF native interface"
125 for chipsets / "South Bridges" supporting low-power modes. Such
128 - Partial: The Phy logic is powered but is in a reduced power
131 - Slumber: The Phy logic is powered but is in an even lower power
134 - DevSleep: The Phy logic may be powered down. The exit latency from
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H A Dpata_mpiix.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_mpiix.c - Intel MPIIX PATA for new ATA layer
4 * (C) 2005-2006 Red Hat Inc
15 * be IDE class PCI. This requires slightly non-standard probe logic compared
20 * PATA history into the clean libata layer.
51 struct ata_port *ap = link->ap; in mpiix_pre_reset()
52 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in mpiix_pre_reset()
56 return -ENOENT; in mpiix_pre_reset()
62 * mpiix_set_piomode - set initial PIO mode data
67 * IORDY sample point (2-5 clocks), recovery (1-4 clocks) and whether
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/linux/drivers/gpu/drm/logicvc/
H A Dlogicvc_layer.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-2022 Bootlin
86 struct drm_device *drm_dev = drm_plane->dev; in logicvc_plane_atomic_check()
87 struct logicvc_layer *layer = logicvc_layer(drm_plane); in logicvc_plane_atomic_check() local
96 if (!new_state->crtc) in logicvc_plane_atomic_check()
99 crtc_state = drm_atomic_get_new_crtc_state(new_state->state, in logicvc_plane_atomic_check()
100 new_state->crtc); in logicvc_plane_atomic_check()
102 return -EINVA in logicvc_plane_atomic_check()
140 struct logicvc_layer *layer = logicvc_layer(drm_plane); logicvc_plane_atomic_update() local
237 struct logicvc_layer *layer = logicvc_layer(drm_plane); logicvc_plane_atomic_disable() local
260 logicvc_layer_buffer_find_setup(struct logicvc_drm * logicvc,struct logicvc_layer * layer,struct drm_plane_state * state,struct logicvc_layer_buffer_setup * setup) logicvc_layer_buffer_find_setup() argument
353 logicvc_layer_formats_lookup(struct logicvc_layer * layer) logicvc_layer_formats_lookup() argument
383 logicvc_layer_config_parse(struct logicvc_drm * logicvc,struct logicvc_layer * layer) logicvc_layer_config_parse() argument
435 struct logicvc_layer *layer; logicvc_layer_get_from_index() local
447 struct logicvc_layer *layer; logicvc_layer_get_from_type() local
466 struct logicvc_layer *layer = NULL; logicvc_layer_init() local
558 logicvc_layer_fini(struct logicvc_drm * logicvc,struct logicvc_layer * layer) logicvc_layer_fini() argument
569 struct logicvc_layer *layer; logicvc_layers_attach_crtc() local
586 struct logicvc_layer *layer; logicvc_layers_init() local
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H A Dlogicvc_of.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-2022 Bootlin
14 { "lvds-4bits", LOGICVC_DISPLAY_INTERFACE_LVDS_4BITS },
15 { "lvds-3bits", LOGICVC_DISPLAY_INTERFACE_LVDS_3BITS },
33 { "layer", LOGICVC_LAYER_ALPHA_LAYER },
40 .name = "xylon,display-interface",
48 .name = "xylon,display-colorspace",
56 .name = "xylon,display-depth",
60 .name = "xylon,row-stride",
67 .name = "xylon,background-layer",
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H A Dlogicvc_layer.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2019-2022 Bootlin
32 bool primary; member
53 struct logicvc_layer *layer,
H A Dlogicvc_mode.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-2022 Bootlin
33 struct drm_device *drm_dev = &logicvc->drm_dev; in logicvc_mode_init()
34 struct drm_mode_config *mode_config = &drm_dev->mode_config; in logicvc_mode_init()
39 ret = drm_vblank_init(drm_dev, mode_config->num_crtc); in logicvc_mode_init()
47 drm_err(drm_dev, "Failed to get primary layer\n"); in logicvc_mode_init()
48 return -EINVAL; in logicvc_mode_init()
51 preferred_depth = layer_primary->formats->depth; in logicvc_mode_init()
54 if (layer_primary->formats->alpha) in logicvc_mode_init()
57 mode_config->min_width = 64; in logicvc_mode_init()
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/linux/drivers/gpu/drm/fsl-dcu/
H A Dfsl_dcu_drm_plane.c1 // SPDX-License-Identifier: GPL-2.0-or-later
26 struct fsl_dcu_drm_device *fsl_dev = plane->dev->dev_private; in fsl_dcu_drm_plane_index()
27 unsigned int total_layer = fsl_dev->soc->total_layer; in fsl_dcu_drm_plane_index()
32 return total_layer - inde in fsl_dcu_drm_plane_index()
208 struct drm_plane *primary; fsl_dcu_drm_primary_create_plane() local
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/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_layer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
23 if (plane->state) { in sun4i_backend_layer_reset()
24 state = state_to_sun4i_layer_state(plane->state); in sun4i_backend_layer_reset()
26 __drm_atomic_helper_plane_destroy_state(&state->state); in sun4i_backend_layer_reset()
29 plane->state = NULL; in sun4i_backend_layer_reset()
34 __drm_atomic_helper_plane_reset(plane, &state->state); in sun4i_backend_layer_reset()
40 struct sun4i_layer_state *orig = state_to_sun4i_layer_state(plane->state); in sun4i_backend_layer_duplicate_state()
47 __drm_atomic_helper_plane_duplicate_state(plane, &copy->state); in sun4i_backend_layer_duplicate_state()
48 copy->uses_frontend = orig->uses_frontend; in sun4i_backend_layer_duplicate_state()
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/linux/drivers/gpu/drm/arm/
H A Dmalidp_crtc.c1 // SPDX-License-Identifier: GPL-2.0-only
29 struct malidp_hw_device *hwdev = malidp->dev; in malidp_crtc_mode_valid()
35 long rate, req_rate = mode->crtc_clock * 1000; in malidp_crtc_mode_valid()
38 rate = clk_round_rate(hwdev->pxlclk, req_rate); in malidp_crtc_mode_valid()
53 struct malidp_hw_device *hwdev = malidp->dev; in malidp_crtc_atomic_enable()
55 int err = pm_runtime_get_sync(crtc->dev->dev); in malidp_crtc_atomic_enable()
62 drm_display_mode_to_videomode(&crtc->state->adjusted_mode, &vm); in malidp_crtc_atomic_enable()
63 clk_prepare_enable(hwdev->pxlclk); in malidp_crtc_atomic_enable()
66 clk_set_rate(hwdev->pxlclk, crtc->state->adjusted_mode.crtc_clock * 1000); in malidp_crtc_atomic_enable()
68 hwdev->hw->modeset(hwdev, &vm); in malidp_crtc_atomic_enable()
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/linux/include/uapi/linux/
H A Dsctp.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
4 * Copyright (c) 1999-2000 Cisco, Inc.
5 * Copyright (c) 1999-2001 Motorola, Inc.
31 * lksctp developers <linux-sctp@vger.kernel.org>
44 * Ryan Layer <rmlayer@us.ibm.com>
47 * Inaky Perez-Gonzalez <inaky.gonzalez@intel.com>
67 * SCTP <draft-ietf-tsvwg-sctpsocket-07.txt>.
116 /* Options 104-106 are deprecated and removed. Do not use this space */
146 /* PR-SCTP policies */
154 #define __SCTP_PR_INDEX(x) ((x >> 4) - 1)
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/linux/drivers/gpu/drm/kmb/
H A Dkmb_plane.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2018-2020 Intel Corporation
28 /* Conversion (yuv->rgb) matrix from myriadx */
31 1024, -352, -731,
33 -179, 125, -22
573 struct kmb_plane *primary = NULL; kmb_plane_init() local
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/linux/Documentation/firmware-guide/acpi/apei/
H A Doutput_format.rst1 .. SPDX-License-Identifier: GPL-2.0
24 [primary][, containment warning][, reset][, threshold exceeded]\
55 [cache error][, TLB error][, bus error][, micro-architectural error]
81 unknown | no error | single-bit ECC | multi-bit ECC | \
82 single-symbol chipkill ECC | multi-symbol chipkill ECC | master abort | \
101 aer_layer=<aer layer string>, aer_agent=<aer agent string>
106 downstream switch port | PCIe to PCI/PCI-X bridge | \
107 PCI/PCI-X to PCIe bridge | root complex integrated endpoint device | \
121 Replay Timer Timeout | Advisory Non-Fatal
124 <aer layer string> :=
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/linux/Documentation/ABI/testing/
H A Dsysfs-class-tsm2 Contact: linux-coco@lists.linux.dev
7 signals when the PCI layer is able to support establishment of
8 link encryption and other device-security features coordinated
12 Contact: linux-pci@vger.kernel.org
15 the platform TSM, symlink appears. The primary function of this
19 Documentation/ABI/testing/sysfs-devices-pci-host-bridge.
/linux/drivers/s390/net/
H A Dqeth_core_mpc.c1 // SPDX-License-Identifier: GPL-2.0
151 {IPA_RC_L2_UNSUPPORTED_CMD, "Unsupported layer 2 command"},
170 {IPA_RC_IP_TABLE_FULL, "Add Addr IP Table Full - ipv6"}
178 {IPA_RC_UNKNOWN_ERROR, "IPA command failed - reason unknown"},
191 {IPA_RC_SBP_IQD_ANO_DEV_PRIMARY, "Primary bridgeport exists already"},
195 {IPA_RC_SBP_IQD_CURRENT_PRIMARY, "Bridgeport is currently primary"},
202 {IPA_RC_SBP_OSA_ANO_DEV_PRIMARY, "Primary bridgeport exists already"},
206 {IPA_RC_SBP_OSA_CURRENT_PRIMARY, "Bridgeport is currently primary"},
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/linux/drivers/gpu/drm/arm/display/komeda/
H A Dkomeda_plane.c1 // SPDX-License-Identifier: GPL-2.0
20 struct komeda_plane *kplane = to_kplane(st->plane); in komeda_plane_init_data_flow()
21 struct drm_framebuffer *fb = st->fb; in komeda_plane_init_data_flow()
22 const struct komeda_format_caps *caps = to_kfb(fb)->format_caps; in komeda_plane_init_data_flow()
23 struct komeda_pipeline *pipe = kplane->layer->base.pipeline; in komeda_plane_init_data_flow()
27 dflow->blending_zorder = st->normalized_zpos; in komeda_plane_init_data_flow()
28 if (pipe == to_kcrtc(st->crtc)->master) in komeda_plane_init_data_flow()
29 dflow->blending_zorder -= kcrtc_st->max_slave_zorder; in komeda_plane_init_data_flow()
30 if (dflow->blending_zorder < 0) { in komeda_plane_init_data_flow()
32 st->plane->name, st->normalized_zpos, in komeda_plane_init_data_flow()
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/linux/Documentation/arch/s390/
H A Dcds.rst9 - Ingo Adlung
10 - Cornelia Huck
12 Copyright, IBM Corp. 1999-2002
21 processing, shared versus non-shared interrupt processing, DMA versus port
30 Operation manual (IBM Form. No. SA22-7201).
33 functional layer was introduced that provides generic I/O access methods to
36 The common device support layer comprises the I/O support routines defined
42 described in Documentation/arch/s390/driver-model.rst.
49 * All drivers must define a ccw_driver (see driver-model.txt) and the associated
56 * The channel device layer is gone.
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/linux/drivers/parisc/
H A Dpdc_stable.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Thibaut VARENE <varenet@parisc-linux.org>
14 * all) PA-RISC machines should have them. Anyway, for safety reasons, the
18 * One last word: there's one path we can always count on: the primary path.
19 * Anything above 224 bytes is used for 'osdep2' OS-dependent storage area.
21 * The first OS-dependent area should always be available. Obviously, this is
24 * NOTE: We do not handle the 2 bytes OS-dep area at 0x5D, nor the first
26 * sacrificed: -ETOOLAZY :P
29 * - write: root only
30 * - read: (reading triggers PDC calls) ? root only : everyone
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/linux/include/net/sctp/
H A Dcommand.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1999-2001 Cisco, Motorola
12 * lksctp developers <linux-sctp@vger.kernel.org>
39 SCTP_CMD_CHUNK_ULP, /* Send a chunk to the sockets layer. */
40 SCTP_CMD_EVENT_ULP, /* Send a notification to the sockets layer. */
55 SCTP_CMD_COOKIEECHO_RESTART, /* High level, do cookie-echo timer work. */
73 SCTP_CMD_SETUP_T2, /* Hi-level, setup T2-shutdown parms. */
82 SCTP_CMD_DEL_NON_PRIMARY, /* Removes non-primary peer transports. */
83 SCTP_CMD_T3_RTX_TIMERS_STOP, /* Stops T3-rtx pending timers */
84 SCTP_CMD_FORCE_PRIM_RETRAN, /* Forces retrans. over primary path. */
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/linux/include/uapi/linux/dvb/
H A Dfrontend.h1 /* SPDX-License-Identifier: LGPL-2.1+ WITH Linux-syscall-note */
18 * enum fe_caps - Frontend capabilities
23 * @FE_CAN_INVERSION_AUTO: Can auto-detect frequency spectral
33 * @FE_CAN_FEC_AUTO: Can auto-detect FEC
35 * @FE_CAN_QAM_16: Supports 16-QAM modulation
36 * @FE_CAN_QAM_32: Supports 32-QAM modulation
37 * @FE_CAN_QAM_64: Supports 64-QAM modulation
38 * @FE_CAN_QAM_128: Supports 128-QAM modulation
39 * @FE_CAN_QAM_256: Supports 256-QAM modulation
40 * @FE_CAN_QAM_AUTO: Can auto-detect QAM modulation
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/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_rm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
31 * dpu_rm_init - Read hardware catalog and create reservation tracking objects
38 * @return: 0 on Success otherwise -ERROR
50 return -EINVAL; in dpu_rm_init()
56 rm->has_legacy_ctls = (cat->mdss_ver->core_major_ver < 5); in dpu_rm_init()
59 for (i = 0; i < cat->mixer_count; i++) { in dpu_rm_init()
61 const struct dpu_lm_cfg *lm = &cat->mixer[i]; in dpu_rm_init()
63 hw = dpu_hw_lm_init(dev, lm, mmio, cat->mdss_ver); in dpu_rm_init()
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/linux/Documentation/filesystems/fuse/
H A Dfuse-passthrough.rst1 .. SPDX-License-Identifier: GPL-2.0
55 discussed and worked on. The primary reasons for this restriction are detailed
59 ----------------------------------
64 associated with a kernel-internal ``struct fuse_backing`` object, which holds a
89 denial-of-service (DoS) by exhausting system-wide file resources.
99 --------------------------------------
107 lower layer that is a FUSE filesystem.
115 filesystem stacking depth (``sb->s_stack_depth`` and ``fc->max_stack_depth``).
121 The ``CAP_SYS_ADMIN`` requirement provides an additional layer of security,
126 ------------------------
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