Home
last modified time | relevance | path

Searched +full:latched +full:- +full:gpios (Results 1 – 14 of 14) sorted by relevance

/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-latch.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-latch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sascha Hauer <s.hauer@pengutronix.de>
14 other GPIOs, like this:
16 CLK0 ----------------------. ,--------.
17 CLK1 -------------------. `--------|> #0 |
19 OUT0 ----------------+--|-----------|D0 Q0|-----|<
20 OUT1 --------------+-|--|-----------|D1 Q1|-----|<
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dti,tlv320adcx140.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter
11 - Andrew Davis <afd@ti.com>
14 The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital
15 PDM microphones recording), high-performance audio, analog-to-digital
28 - ti,tlv320adc3140
29 - ti,tlv320adc5140
30 - ti,tlv320adc6140
[all …]
/linux/Documentation/devicetree/bindings/input/touchscreen/
H A Deeti.txt4 - compatible: should be "eeti,exc3000-i2c"
5 - reg: I2C address of the chip. Should be set to <0xa>
6 - interrupts: interrupt to which the chip is connected
9 - attn-gpios: A handle to a GPIO to check whether interrupt is still
10 latched. This is necessary for platforms that lack
11 support for level-triggered IRQs.
16 - touchscreen-inverted-x
17 - touchscreen-inverted-y
18 - touchscreen-swapped-x-y
22 i2c-master {
[all …]
/linux/Documentation/devicetree/bindings/iio/resolver/
H A Dadi,ad2s1210.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AD2S1210 Resolver-to-Digital Converter
10 - Michael Hennerich <michael.hennerich@analog.com>
13 The AD2S1210 is a complete 10-bit to 16-bit resolution tracking
14 resolver-to-digital converter, integrating an on-board programmable
23 selected by the A0 and A1 input pins. In normal mode, data is latched by
29 0 0 Normal mode - position output
30 0 1 Normal mode - velocity output
[all …]
/linux/Documentation/devicetree/bindings/iio/dac/
H A Dadi,ltc2664.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
11 - Kim Seer Paller <kimseer.paller@analog.com>
14 Analog Devices LTC2664 4 channel, 12-/16-Bit, +-10V DAC
15 https://www.analog.com/media/en/technical-documentation/data-sheets/2664fa.pdf
20 - adi,ltc2664
25 spi-max-frequency:
28 vcc-supply:
[all …]
/linux/drivers/pinctrl/qcom/
H A Dpinctrl-msm.c1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <linux/pinctrl/pinconf-generic.h>
32 #include "../pinctrl-utils.h"
34 #include "pinctrl-msm.h"
41 * struct msm_pinctrl - state for a pinctrl-msm device
89 return readl(pctrl->regs[g->tile] + g->name##_reg); \
94 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
106 u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0; in MSM_ACCESSOR()
115 return pctrl->soc->ngroups; in msm_get_groups_count()
123 return pctrl->soc->groups[group].grp.name; in msm_get_group_name()
[all …]
/linux/drivers/gpio/
H A Dgpio-latch.c1 // SPDX-License-Identifier: GPL-2.0
10 * CLK0 ----------------------. ,--------.
11 * CLK1 -------------------. `--------|> #0 |
13 * OUT0 ----------------+--|-----------|D0 Q0|-----|<
14 * OUT1 --------------+-|--|-----------|D1 Q1|-----|<
15 * OUT2 ------------+-|-|--|-----------|D2 Q2|-----|<
16 * OUT3 ----------+-|-|-|--|-----------|D3 Q3|-----|<
17 * OUT4 --------+-|-|-|-|--|-----------|D4 Q4|-----|<
18 * OUT5 ------+-|-|-|-|-|--|-----------|D5 Q5|-----|<
19 * OUT6 ----+-|-|-|-|-|-|--|-----------|D6 Q6|-----|<
[all …]
H A Dgpio-ich.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver
19 * Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
34 {0x00, 0x30, 0x40}, /* USE_SEL[1-3] offsets */
35 {0x04, 0x34, 0x44}, /* IO_SEL[1-3] offsets */
36 {0x0c, 0x38, 0x48}, /* LVL[1-3] offsets */
54 #define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start)
55 #define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start)
91 struct ichx_desc *desc; /* Pointer to chipset-specific description */
97 static int modparam_gpiobase = -1; /* dynamic */
[all …]
H A Dgpio-pca953x.c1 // SPDX-License-Identifier: GPL-2.0-only
32 #include <linux/pinctrl/pinconf-generic.h>
135 { "irq-gpios", &pca953x_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER },
161 * relative. Since first controller (gpio-sch.c) and
162 * second (gpio-dwapb.c) are at the fixed bases, we may
184 #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)
235 return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); in pca953x_bank_shift()
257 * - Standard set, below 0x40, each port can be replicated up to 8 times
258 * - PCA953x standard
263 * - PCA957x with mixed up registers
[all …]
H A Dgpio-mvebu.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
19 * - the basic variant, called "orion-gpio", with the simplest
21 * non-SMP Discovery systems
22 * - the mv78200 variant for MV78200 Discovery systems. This variant
26 * - the armadaxp variant for Armada XP systems. This variant keeps
28 * interrupts are used, but adds per-CPU cause/edge mask/level mask
29 * registers n a separate memory area for the per-CPU GPIO
73 /* Armada 8k variant gpios register offsets */
[all …]
/linux/drivers/pinctrl/bcm/
H A Dpinctrl-bcm2835.c1 // SPDX-License-Identifier: GPL-2.0+
8 * pinctrl-nomadik.c, please see original file for copyright information
9 * pinctrl-tegra.c, please see original file for copyright information
32 #include <linux/pinctrl/pinconf-generic.h>
39 #include <dt-bindings/pinctrl/bcm2835.h>
41 #define MODULE_NAME "pinctrl-bcm2835"
59 #define GPPUD 0x94 /* Pin Pull-up/down Enable */
60 #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */
61 #define GP_GPIO_PUP_PDN_CNTRL_REG0 0xe4 /* 2711 Pin Pull-up/down select */
241 [IRQ_TYPE_EDGE_RISING] = "edge-rising",
[all …]
/linux/drivers/pinctrl/
H A Dpinctrl-cy8c95x0.c1 // SPDX-License-Identifier: GPL-2.0-only
28 #include <linux/pinctrl/pinconf-generic.h>
69 (CY8C95X0_VIRTUAL + (x) - CY8C95X0_PORTSEL + (p) * MUXED_STRIDE)
92 { "irq-gpios", &cy8c95x0_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER },
117 * Since first controller (gpio-sch.c) and second
118 * (gpio-dwapb.c) are at the fixed bases, we may safely
130 * struct cy8c95x0_pinctrl - driver data
486 return -EINVAL; in cy8c95x0_regmap_update_bits_base()
498 guard(mutex)(&chip->i2c_lock); in cy8c95x0_regmap_update_bits_base()
500 ret = regmap_update_bits_base(chip->regmap, off, mask, val, change, async, force); in cy8c95x0_regmap_update_bits_base()
[all …]
/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-phy-v2.c125 #include "xgbe-common.h"
149 /* Rate-change complete wait/retry count */
276 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \
277 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
284 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
285 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
306 /* Re-driver related definitions */
375 /* Re-driver support */
399 return pdata->i2c_if.i2c_xfer(pdata, i2c_op); in xgbe_phy_i2c_xfer()
405 struct xgbe_phy_data *phy_data = pdata->phy_data; in xgbe_phy_redrv_write()
[all …]
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_link.c1 /* Copyright 2008-2013 Broadcom Corporation
8 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
43 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
205 (_phy)->def_md_devad, \
211 (_phy)->def_md_devad, \
239 * bnx2x_check_lfa - This function checks if link reinitialization is required,
251 struct bnx2x *bp = params->bp; in bnx2x_check_lfa()
254 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
257 /* NOTE: must be first condition checked - in bnx2x_check_lfa()
262 REG_WR(bp, params->lfa_base + in bnx2x_check_lfa()
[all …]