Searched +full:latch +full:- +full:ck (Results 1 – 3 of 3) sorted by relevance
1 /* SPDX-License-Identifier: GPL-2.0-only */6 * Tero Kristo (t-kristo@ti.com)16 s8 latch; member32 s8 latch; member87 #define CLK(dev, con, ck) \ argument93 .clk = ck, \142 * struct ti_dt_clk - OMAP DT clock alias declarations
3 * Copyright (c) 2007-2013 Broadcom Corporation13 * R - Read only14 * RC - Clear on read15 * RW - Read/Write16 * ST - Statistics register (clear on read)17 * W - Write only18 * WB - Wide bus register - the size is over 32 bits and it should be20 * WR - Write Clear (write 1 to clear the bit)32 /* [RW 1] Initiate the ATC array - reset all the valid bits */56 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -[all …]
1 // SPDX-License-Identifier: GPL-2.02 /* Copyright(c) 1999 - 2018 Intel Corporation. */36 static int debug = -1;113 * __ew32_prepare - prepare to write to MAC CSR register on certain parts128 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) in __ew32_prepare()134 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) in __ew32()137 writel(val, hw->hw_addr + reg); in __ew32()141 * e1000_regdump - register printout routine151 switch (reginfo->ofs) { in e1000_regdump()165 pr_info("%-15s %08x\n", in e1000_regdump()[all …]