Searched +full:latch +full:- +full:ck (Results 1 – 3 of 3) sorted by relevance
1 /* SPDX-License-Identifier: GPL-2.0-only */6 * Tero Kristo (t-kristo@ti.com)16 s8 latch; member32 s8 latch; member87 #define CLK(dev, con, ck) \ argument93 .clk = ck, \142 * struct ti_dt_clk - OMAP DT clock alias declarations
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Chaotian Jing <chaotian.jing@mediatek.com>11 - Wenbin Mei <wenbin.mei@mediatek.com>16 - enum:17 - mediatek,mt2701-mmc18 - mediatek,mt2712-mmc19 - mediatek,mt6779-mmc[all …]
3 * Copyright (c) 2007-2013 Broadcom Corporation13 * R - Read only14 * RC - Clear on read15 * RW - Read/Write16 * ST - Statistics register (clear on read)17 * W - Write only18 * WB - Wide bus register - the size is over 32 bits and it should be20 * WR - Write Clear (write 1 to clear the bit)32 /* [RW 1] Initiate the ATC array - reset all the valid bits */56 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -[all …]