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/linux/Documentation/devicetree/bindings/display/bridge/
H A Danalogix,anx7625.yaml72 analogix,lane1-swing:
77 an array of swing register setting for DP tx lane1 PHY.
78 DP TX lane1 swing register setting same with lane0
150 analogix,lane1-swing = /bits/ 8 <0x14 0x54 0x64 0x74>;
/linux/Documentation/devicetree/bindings/phy/
H A Dairoha,en7581-pcie-phy.yaml23 - description: PCIE lane1 base address
25 - description: PCIE lane1 detection time base address
H A Dqcom,msm8996-qmp-pcie-phy.yaml88 - lane1
H A Dfsl,imx8qm-hsio.yaml55 | | Lane0| Lane1| Lane2|
/linux/Documentation/devicetree/bindings/pci/
H A Dpci-armada8k.txt25 Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for
/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c188 * lane1: PCIe/GbE0 PHY Configuration 1
209 * lane1: PCIe/GbE0 PHY Status 1
219 /* bit0: 0: Lane1 is GbE0; 1: Lane1 is PCIe */
501 /* PCIE must be in Lane1 */ in mvebu_a3700_comphy_set_phy_selector()
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8186-corsola-steelix.dtsi64 analogix,lane1-swing = /bits/ 8 <0x70 0x30>;
/linux/drivers/gpu/drm/amd/display/include/
H A Dgrph_object_ctrl_defs.h243 uint8_t lane1:2; /* Mapping for lane 1 */ member
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-dphy-rx0.c212 /* HS RX Control of lane1 */ in rk_dphy_enable()
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3568.dtsi192 /* bifurcation; lane1 when using 1+1 */
/linux/drivers/net/ethernet/ti/
H A Dnetcp_xgbepcsr.c258 /* For 2 lane Phy-B, lane0 is actually lane1 */ in netcp_xgbe_serdes_write_tbus_addr()
/linux/drivers/ufs/host/
H A Dufs-hisi.c62 dev_err(hba->dev, "%s: invalid TX_FSM_STATE, lane0 = %d, lane1 = %d\n", in ufs_hisi_check_hibern8()
/linux/drivers/gpu/drm/msm/registers/display/
H A Ddsi.xml99 <bitfield name="LANE1" pos="5" type="boolean"/>
/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_training.c116 lt_result = "CR failed lane1"; in dp_log_training_result()
/linux/drivers/gpu/drm/bridge/analogix/
H A Danx7625.c1655 num_regs = of_property_read_variable_u8_array(dev->of_node, "analogix,lane1-swing", in anx7625_get_swing_setting()
/linux/drivers/gpu/drm/radeon/
H A Datombios.h4113 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: …
/linux/drivers/gpu/drm/amd/include/
H A Datombios.h4605 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: …