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/linux/Documentation/devicetree/bindings/phy/
H A Dphy-rockchip-usbdp.yaml64 3>;", assuming DP lane0 on Type-C phy lane2, DP lane1 on Type-C phy
66 <0, 1, 2, 3>;", assuming DP lane0 on Type-C phy lane0, DP lane1 on Type-C
67 phy lane1, DP lane2 on Type-C phy lane2, DP lane3 on Type-C phy lane3. If
H A Dairoha,en7581-pcie-phy.yaml23 - description: PCIE lane1 base address
25 - description: PCIE lane1 detection time base address
H A Dqcom,msm8996-qmp-pcie-phy.yaml88 - lane1
H A Dfsl,imx8qm-hsio.yaml55 | | Lane0| Lane1| Lane2|
/linux/arch/arm64/boot/dts/airoha/
H A Den7581.dtsi223 reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
266 reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c188 * lane1: PCIe/GbE0 PHY Configuration 1
209 * lane1: PCIe/GbE0 PHY Status 1
219 /* bit0: 0: Lane1 is GbE0; 1: Lane1 is PCIe */
501 /* PCIE must be in Lane1 */ in mvebu_a3700_comphy_set_phy_selector()
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8186-corsola-steelix.dtsi64 analogix,lane1-swing = /bits/ 8 <0x70 0x30>;
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-8040-mcbin.dtsi188 phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
H A Darmada-8040-puzzle-m801.dts521 phy-names = "cp1-pcie0-x2-lane0-phy", "cp1-pcie0-x2-lane1-phy";
/linux/drivers/gpu/drm/amd/display/include/
H A Dgrph_object_ctrl_defs.h248 uint8_t lane1:2; /* Mapping for lane 1 */ member
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-dphy-rx0.c212 /* HS RX Control of lane1 */ in rk_dphy_enable()
/linux/drivers/net/ethernet/ti/
H A Dnetcp_xgbepcsr.c258 /* For 2 lane Phy-B, lane0 is actually lane1 */ in netcp_xgbe_serdes_write_tbus_addr()
/linux/lib/zstd/compress/
H A Dzstd_compress.c6917 * we use _mm256_permute4x64_epi64(..., 0xE8) to move lane2 into lane1,
7004 * Lane1 = 0 in convertSequences_noRepcodes()
7009 /* Permute 64-bit lanes => move Lane2 down into Lane1. */ in convertSequences_noRepcodes()
7012 * Now the lower 16 bytes (Lane0+Lane1) = [seq0, seq1]. in convertSequences_noRepcodes()
/linux/drivers/gpu/drm/radeon/
H A Datombios.h4112 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: …
/linux/drivers/gpu/drm/amd/include/
H A Datombios.h4605 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: …