| /linux/Documentation/devicetree/bindings/soc/ti/ |
| H A D | ti,j721e-system-controller.yaml | 95 <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
96 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
97 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
98 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
100 /* SERDES4 lane0/1/2/3 select */
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| /linux/Documentation/devicetree/bindings/display/bridge/ |
| H A D | analogix,anx7625.yaml | 45 analogix,lane0-swing:
50 an array of swing register setting for DP tx lane0 PHY.
78 DP TX lane1 swing register setting same with lane0
79 swing, please refer lane0-swing property description.
149 analogix,lane0-swing = /bits/ 8 <0x14 0x54 0x64 0x74>;
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| /linux/drivers/phy/amlogic/ |
| H A D | phy-meson-g12a-usb3-pcie.c | 215 * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus in phy_g12a_usb3_init()
228 * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0 in phy_g12a_usb3_init()
229 * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1 in phy_g12a_usb3_init()
230 * LANE0.RX_OVRD_IN_HI.RX_EQ set to 3 in phy_g12a_usb3_init()
231 * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1 in phy_g12a_usb3_init()
248 * LANE0.TX_OVRD_DRV_LO.PREEMPH set to 22 in phy_g12a_usb3_init()
249 * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 127 in phy_g12a_usb3_init()
250 * LANE0.TX_OVRD_DRV_LO.EN set to 1. in phy_g12a_usb3_init()
|
| /linux/drivers/phy/qualcomm/ |
| H A D | phy-qcom-ipq806x-usb.c | 341 * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus mode in qcom_ipq806x_usb_ss_phy_init()
364 * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0 in qcom_ipq806x_usb_ss_phy_init()
365 * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1 in qcom_ipq806x_usb_ss_phy_init()
366 * LANE0.RX_OVRD_IN_HI.RX_EQ set based on SoC version in qcom_ipq806x_usb_ss_phy_init()
367 * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1 in qcom_ipq806x_usb_ss_phy_init()
385 * LANE0.TX_OVRD_DRV_LO.PREEMPH set based on SoC version in qcom_ipq806x_usb_ss_phy_init()
386 * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 110 in qcom_ipq806x_usb_ss_phy_init()
387 * LANE0.TX_OVRD_DRV_LO.EN set to 1. in qcom_ipq806x_usb_ss_phy_init()
|
| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | airoha,en7581-pcie-phy.yaml | 22 - description: PCIE lane0 base address
24 - description: PCIE lane0 detection time base address
|
| H A D | qcom,msm8996-qmp-pcie-phy.yaml | 87 - lane0
|
| H A D | fsl,imx8qm-hsio.yaml | 55 | | Lane0| Lane1| Lane2|
|
| /linux/drivers/phy/freescale/ |
| H A D | phy-fsl-imx8qm-hsio.c | 370 * Except the phy_off, the bit-offset of lane2 is same to lane0. in imx_hsio_power_on()
371 * Merge the lane0 and lane2 bit-operations together. in imx_hsio_power_on()
433 * to lane0. Merge the lane0 and lane2 bit-operations in imx_hsio_power_off()
|
| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | pci-armada8k.txt | 25 Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for
|
| /linux/arch/arm64/boot/dts/ti/ |
| H A D | k3-j722s-main.dtsi | 224 mux-reg-masks = <0x00 0x3>, /* SERDES0 lane0 select */
225 <0x10 0x3>; /* SERDES1 lane0 select */
|
| H A D | k3-j721e-main.dtsi | 51 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
52 <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */
53 <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */
54 <0x30 0x3>, <0x34 0x3>, /* SERDES3 lane0/1 select */
55 <0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */
|
| H A D | k3-j784s4-main.dtsi | 88 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
90 <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */
92 <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */
|
| /linux/drivers/phy/marvell/ |
| H A D | phy-mvebu-a3700-comphy.c | 187 * lane0: USB3/GbE1 PHY Configuration 1
208 * lane0: USB3/GbE1 PHY Status 1
221 /* bit4: 0: Lane0 is GbE1; 1: Lane0 is USB3 */
223 /* bit8: 0: Lane0 is USB3 instead of GbE1, Lane2 is SATA; 1: Lane2 is USB3 */
|
| /linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt8186-corsola-steelix.dtsi | 63 analogix,lane0-swing = /bits/ 8 <0x70 0x30>;
|
| /linux/drivers/phy/starfive/ |
| H A D | phy-jh7110-dphy-rx.c | 56 * [clk lane0, data lane 0, data lane 1, data lane 2, date lane 3, clk lane 1]
|
| /linux/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3588-friendlyelec-cm3588-nas.dts | 415 /* 1. M.2 socket, CON13: pcie30phy port0 lane0, @fe150000 */
426 /* 3. M.2 socket, CON15: pcie30phy port1 lane0, @fe160000 */
|
| /linux/drivers/gpu/drm/amd/display/include/ |
| H A D | grph_object_ctrl_defs.h | 242 uint8_t lane0:2; /* Mapping for lane 0 */ member
|
| /linux/arch/arm64/boot/dts/marvell/ |
| H A D | armada-8040-mcbin.dtsi | 188 phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
|
| H A D | armada-8040-puzzle-m801.dts | 521 phy-names = "cp1-pcie0-x2-lane0-phy", "cp1-pcie0-x2-lane1-phy";
|
| /linux/drivers/phy/rockchip/ |
| H A D | phy-rockchip-dphy-rx0.c | 210 /* HS RX Control of lane0 */ in rk_dphy_enable()
|
| /linux/drivers/net/ethernet/ti/ |
| H A D | netcp_xgbepcsr.c | 258 /* For 2 lane Phy-B, lane0 is actually lane1 */ in netcp_xgbe_serdes_write_tbus_addr()
|
| /linux/drivers/ufs/host/ |
| H A D | ufs-hisi.c | 62 dev_err(hba->dev, "%s: invalid TX_FSM_STATE, lane0 = %d, lane1 = %d\n", in ufs_hisi_check_hibern8()
|
| /linux/drivers/gpu/drm/msm/registers/display/ |
| H A D | dsi.xml | 98 <bitfield name="LANE0" pos="4" type="boolean"/>
|
| /linux/drivers/gpu/drm/rockchip/ |
| H A D | dw-mipi-dsi-rockchip.c | 1259 * Set clock lane and hsfreqrange by lane0(test code 0x44) in dw_mipi_dsi_dphy_power_on()
|
| /linux/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| H A D | link_dp_training.c | 113 lt_result = "CR failed lane0"; in dp_log_training_result()
|