| /linux/Documentation/devicetree/bindings/soc/ti/ |
| H A D | ti,j721e-system-controller.yaml | 113 <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
114 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
115 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
116 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
118 /* SERDES4 lane0/1/2/3 select */
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| /linux/drivers/phy/amlogic/ |
| H A D | phy-meson-g12a-usb3-pcie.c | 215 * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus in phy_g12a_usb3_init()
228 * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0 in phy_g12a_usb3_init()
229 * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1 in phy_g12a_usb3_init()
230 * LANE0.RX_OVRD_IN_HI.RX_EQ set to 3 in phy_g12a_usb3_init()
231 * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1 in phy_g12a_usb3_init()
248 * LANE0.TX_OVRD_DRV_LO.PREEMPH set to 22 in phy_g12a_usb3_init()
249 * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 127 in phy_g12a_usb3_init()
250 * LANE0.TX_OVRD_DRV_LO.EN set to 1. in phy_g12a_usb3_init()
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| /linux/drivers/phy/qualcomm/ |
| H A D | phy-qcom-ipq806x-usb.c | 341 * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus mode in qcom_ipq806x_usb_ss_phy_init()
364 * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0 in qcom_ipq806x_usb_ss_phy_init()
365 * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1 in qcom_ipq806x_usb_ss_phy_init()
366 * LANE0.RX_OVRD_IN_HI.RX_EQ set based on SoC version in qcom_ipq806x_usb_ss_phy_init()
367 * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1 in qcom_ipq806x_usb_ss_phy_init()
385 * LANE0.TX_OVRD_DRV_LO.PREEMPH set based on SoC version in qcom_ipq806x_usb_ss_phy_init()
386 * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 110 in qcom_ipq806x_usb_ss_phy_init()
387 * LANE0.TX_OVRD_DRV_LO.EN set to 1. in qcom_ipq806x_usb_ss_phy_init()
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| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | phy-rockchip-usbdp.yaml | 64 3>;", assuming DP lane0 on Type-C phy lane2, DP lane1 on Type-C phy
66 <0, 1, 2, 3>;", assuming DP lane0 on Type-C phy lane0, DP lane1 on Type-C
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| H A D | airoha,en7581-pcie-phy.yaml | 22 - description: PCIE lane0 base address
24 - description: PCIE lane0 detection time base address
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| H A D | qcom,msm8996-qmp-pcie-phy.yaml | 87 - lane0
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| H A D | fsl,imx8qm-hsio.yaml | 55 | | Lane0| Lane1| Lane2|
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| /linux/arch/arm64/boot/dts/airoha/ |
| H A D | en7581.dtsi | 223 reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
266 reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
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| /linux/drivers/phy/marvell/ |
| H A D | phy-mvebu-a3700-comphy.c | 187 * lane0: USB3/GbE1 PHY Configuration 1
208 * lane0: USB3/GbE1 PHY Status 1
221 /* bit4: 0: Lane0 is GbE1; 1: Lane0 is USB3 */
223 /* bit8: 0: Lane0 is USB3 instead of GbE1, Lane2 is SATA; 1: Lane2 is USB3 */
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| /linux/drivers/phy/apple/ |
| H A D | atc.c | 879 const int lane0 = atcphy->swap_lanes ? 1 : 0; in atcphy_apply_tunables() local
894 apple_tunable_apply(atcphy->regs.core, atcphy->tunables.lane_usb3[lane0]); in atcphy_apply_tunables()
899 apple_tunable_apply(atcphy->regs.core, atcphy->tunables.lane_dp[lane0]); in atcphy_apply_tunables()
910 apple_tunable_apply(atcphy->regs.core, atcphy->tunables.lane_usb4[lane0]); in atcphy_apply_tunables()
2187 { "apple,tunable-lane0-usb", &atcphy->tunables.lane_usb3[0], atcphy->res.core }, in atcphy_load_tunables()
2189 { "apple,tunable-lane0-cio", &atcphy->tunables.lane_usb4[0], atcphy->res.core }, in atcphy_load_tunables()
2191 { "apple,tunable-lane0-dp", &atcphy->tunables.lane_dp[0], atcphy->res.core }, in atcphy_load_tunables()
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| /linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt8186-corsola-steelix.dtsi | 63 analogix,lane0-swing = /bits/ 8 <0x70 0x30>;
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| /linux/drivers/phy/starfive/ |
| H A D | phy-jh7110-dphy-rx.c | 56 * [clk lane0, data lane 0, data lane 1, data lane 2, date lane 3, clk lane 1]
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| /linux/arch/arm64/boot/dts/marvell/ |
| H A D | armada-8040-mcbin.dtsi | 188 phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
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| H A D | armada-8040-puzzle-m801.dts | 521 phy-names = "cp1-pcie0-x2-lane0-phy", "cp1-pcie0-x2-lane1-phy";
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| /linux/drivers/phy/rockchip/ |
| H A D | phy-rockchip-dphy-rx0.c | 210 /* HS RX Control of lane0 */ in rk_dphy_enable()
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| /linux/drivers/phy/spacemit/ |
| H A D | phy-k3-common.c | 279 /* pll_reg1 of lane0, disable SSC: pll[27:24] = 0 */ in k3_pcie_phy_init()
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| /linux/drivers/net/ethernet/ti/ |
| H A D | netcp_xgbepcsr.c | 258 /* For 2 lane Phy-B, lane0 is actually lane1 */ in netcp_xgbe_serdes_write_tbus_addr()
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| /linux/drivers/pci/controller/ |
| H A D | pcie-mediatek-gen3.c | 1418 .id[0] = "phy-lane0",
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| /linux/lib/zstd/compress/ |
| H A D | zstd_compress.c | 6970 * Explanation of 0xE8 = 11101000b => [lane0, lane2, lane2, lane3]. in convertSequences_noRepcodes()
6971 * So the lower 128 bits become [lane0, lane2] => combining seq0 and seq1. in convertSequences_noRepcodes()
7003 * Lane0 = seq0's 8 bytes in convertSequences_noRepcodes()
7012 * Now the lower 16 bytes (Lane0+Lane1) = [seq0, seq1]. in convertSequences_noRepcodes()
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| /linux/drivers/phy/samsung/ |
| H A D | phy-exynos5-usbdrd.c | 1132 * register LANE0.TX_DEBUG which is internal to PHY. in exynos5420_usbdrd_phy_calibrate()
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | atombios.h | 4113 //Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: …
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| /linux/drivers/gpu/drm/amd/include/ |
| H A D | atombios.h | 4606 //Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: …
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