xref: /linux/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml (revision 11efc1cb7016e300047822fd60e0f4b4158bd56d) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright (C) 2020 SiFive, Inc.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/cache/sifive,ccache0.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: SiFive Composable Cache Controller
9
10maintainers:
11  - Paul Walmsley <paul.walmsley@sifive.com>
12
13description:
14  The SiFive Composable Cache Controller is used to provide access to fast copies
15  of memory for masters in a Core Complex. The Composable Cache Controller also
16  acts as directory-based coherency manager.
17  All the properties in ePAPR/DeviceTree specification applies for this platform.
18
19select:
20  properties:
21    compatible:
22      contains:
23        enum:
24          - sifive,ccache0
25          - sifive,fu540-c000-ccache
26          - sifive,fu740-c000-ccache
27
28  required:
29    - compatible
30
31properties:
32  compatible:
33    oneOf:
34      - items:
35          - enum:
36              - sifive,ccache0
37              - sifive,fu540-c000-ccache
38              - sifive,fu740-c000-ccache
39          - const: cache
40      - items:
41          - enum:
42              - eswin,eic7700-l3-cache
43              - starfive,jh7100-ccache
44              - starfive,jh7110-ccache
45          - const: sifive,ccache0
46          - const: cache
47      - items:
48          - const: microchip,mpfs-ccache
49          - const: sifive,fu540-c000-ccache
50          - const: cache
51      - items:
52          - const: microchip,pic64gx-ccache
53          - const: microchip,mpfs-ccache
54          - const: sifive,fu540-c000-ccache
55          - const: cache
56
57  cache-block-size:
58    const: 64
59
60  cache-level:
61    enum: [2, 3]
62
63  cache-sets:
64    enum: [1024, 2048, 4096]
65
66  cache-size:
67    enum: [2097152, 4194304]
68
69  cache-unified: true
70
71  interrupts:
72    minItems: 3
73    items:
74      - description: DirError interrupt
75      - description: DataError interrupt
76      - description: DataFail interrupt
77      - description: DirFail interrupt
78
79  reg:
80    maxItems: 1
81
82  next-level-cache: true
83
84  memory-region:
85    maxItems: 1
86    description: |
87      The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
88      The reserved memory node should be defined as per the bindings in reserved-memory.txt.
89
90allOf:
91  - $ref: /schemas/cache-controller.yaml#
92
93  - if:
94      properties:
95        compatible:
96          contains:
97            enum:
98              - eswin,eic7700-l3-cache
99              - sifive,fu740-c000-ccache
100              - starfive,jh7100-ccache
101              - starfive,jh7110-ccache
102              - microchip,mpfs-ccache
103
104    then:
105      properties:
106        interrupts:
107          description: |
108            Must contain entries for DirError, DataError, DataFail, DirFail signals.
109          minItems: 4
110
111    else:
112      properties:
113        interrupts:
114          description: |
115            Must contain entries for DirError, DataError and DataFail signals.
116          maxItems: 3
117
118  - if:
119      properties:
120        compatible:
121          contains:
122            const: eswin,eic7700-l3-cache
123
124    then:
125      properties:
126        cache-size:
127          const: 4194304
128
129    else:
130      properties:
131        cache-size:
132          const: 2097152
133
134  - if:
135      properties:
136        compatible:
137          contains:
138            enum:
139              - sifive,fu740-c000-ccache
140              - starfive,jh7100-ccache
141              - starfive,jh7110-ccache
142
143    then:
144      properties:
145        cache-sets:
146          const: 2048
147
148  - if:
149      properties:
150        compatible:
151          contains:
152            enum:
153              - microchip,mpfs-ccache
154              - sifive,fu540-c000-ccache
155
156    then:
157      properties:
158        cache-sets:
159          const: 1024
160
161  - if:
162      properties:
163        compatible:
164          contains:
165            enum:
166              - eswin,eic7700-l3-cache
167
168    then:
169      properties:
170        cache-sets:
171          const: 4096
172
173  - if:
174      properties:
175        compatible:
176          contains:
177            const: sifive,ccache0
178
179    then:
180      properties:
181        cache-level:
182          enum: [2, 3]
183
184    else:
185      properties:
186        cache-level:
187          const: 2
188
189additionalProperties: false
190
191required:
192  - compatible
193  - cache-block-size
194  - cache-level
195  - cache-sets
196  - cache-size
197  - cache-unified
198  - interrupts
199  - reg
200
201examples:
202  - |
203    cache-controller@2010000 {
204        compatible = "sifive,fu540-c000-ccache", "cache";
205        cache-block-size = <64>;
206        cache-level = <2>;
207        cache-sets = <1024>;
208        cache-size = <2097152>;
209        cache-unified;
210        reg = <0x2010000 0x1000>;
211        interrupt-parent = <&plic0>;
212        interrupts = <1>,
213                     <2>,
214                     <3>;
215        next-level-cache = <&L25>;
216        memory-region = <&l2_lim>;
217    };
218