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/freebsd/sys/dev/videomode/
H A Dmodelines18 # 640x350 @ 85Hz (VESA) hsync: 37.9kHz
21 # 640x400 @ 85Hz (VESA) hsync: 37.9kHz
24 # 720x400 @ 70Hz (EDID established timing) hsync: 31.47kHz
27 # 720x400 @ 85Hz (VESA) hsync: 37.9kHz
30 # 720x400 @ 88Hz (EDID established timing) hsync: 39.44kHz
33 # 640x480 @ 60Hz (Industry standard) hsync: 31.5kHz
36 # 640x480 @ 72Hz (VESA) hsync: 37.9kHz
39 # 640x480 @ 75Hz (VESA) hsync: 37.5kHz
42 # 640x480 @ 85Hz (VESA) hsync: 43.3kHz
45 # 800x600 @ 56Hz (VESA) hsync: 35.2kHz
[all …]
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dti,j721e-cpb-audio.yaml18 In order to support 48KHz and 44.1KHz family of sampling rates the parent
19 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
20 PLL15 (for 44.1KHz). The same PLLs are used for McASP10's AUXCLK clock via
24 48KHz family:
28 44.1KHz family:
33 48KHz family:
85 - description: Parent for CPB_McASP auxclk (for 48KHz)
86 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
88 - description: Parent for CPB_SCKI clock (for 48KHz)
89 - description: Parent for CPB_SCKI clock (for 44.1KHz)
[all …]
H A Dti,j721e-cpb-ivi-audio.yaml23 In order to support 48KHz and 44.1KHz family of sampling rates the parent clock
24 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
25 44.1KHz). The same PLLs are used for McASP0's AUXCLK clock via different
30 Clocking setup for 48KHz family:
37 Clocking setup for 44.1KHz family:
76 - description: Parent for CPB_McASP auxclk (for 48KHz)
77 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
79 - description: Parent for CPB_SCKI clock (for 48KHz)
80 - description: Parent for CPB_SCKI clock (for 44.1KHz)
[all...]
H A Dti,pcm6240.yaml38 ti,adc3120: Stereo-channel, 768-kHz, Burr-Brown™ audio analog-to-
41 ti,adc5120: 2-Channel, 768-kHz, Burr-Brown™ Audio ADC with 120-dB SNR.
43 ti,adc6120: Stereo-channel, 768-kHz, Burr-Brown™ audio analog-to-
46 ti,dix4192: 216-kHz digital audio converter with Quad-Channel In
52 ti,pcm3120: Automotive, stereo, 106-dB SNR, 768-kHz, low-power
55 ti,pcm3140: Automotive, Quad-Channel, 768-kHz, Burr-Brown™ Audio ADC
58 ti,pcm5120: Automotive, stereo, 120-dB SNR, 768-kHz, low-power
61 ti,pcm5140: Automotive, Quad-Channel, 768-kHz, Burr-Brown™ Audio ADC
64 ti,pcm6120: Automotive, stereo, 123-dB SNR, 768-kHz, low-power
67 ti,pcm6140: Automotive, Quad-Channel, 768-kHz, Burr-Brown™ Audio ADC
[all …]
H A Dst,stm32-sai.yaml152 - description: x8k, SAI parent clock for sampling rates multiple of 8kHz.
153 - description: x11k, SAI parent clock for sampling rates multiple of 11.025kHz.
164 - description: x8k, SAI parent clock for sampling rates multiple of 8kHz.
165 - description: x11k, SAI parent clock for sampling rates multiple of 11.025kHz.
H A Dgtm601.txt5 "option,gtm601" = 8kHz mono
6 "broadmobi,bm818" = 48KHz stereo
/freebsd/contrib/file/magic/scripts/
H A Dcreate_filemagic_flac6 ## >>17 belong&0xfffff0 0x2ee000 \b, 192 kHz
15 ## (16384 kHz = 32 kHz * 512 = 32 * 2^9)
17 ## (22579.2 kHz = 44.1kHz * 512 = 44.1 * 2^9)
20 ## (24576 kHz = 48 kHz * 512 = 48 * 2^9)
53 ## use bc with sed to convert and format Hz to kHz
58 printf -v line ">>17\tbelong&%#-15x\t%#08x\t%s, %s kHz\n" \
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dlpc1850-creg-clk.txt5 32 kHz oscillator driver with power up/down and clock gating. Next
6 is a fixed divider that creates a 1 kHz clock from the 32 kHz osc.
9 The 32 kHz can also be routed to other peripherals to enable low
21 Shall contain a phandle to the fixed 32 kHz crystal.
28 0 1 kHz clock
29 1 32 kHz Oscillator
H A Damlogic,gxbb-aoclkc.txt19 * "ext-32k-0" : external 32kHz reference #0 if any (optional)
20 * "ext-32k-1" : external 32kHz reference #1 if any (optional - gx only)
21 * "ext-32k-2" : external 32kHz reference #2 if any (optional - gx only)
H A Dmaxim,max77686.txt10 The MAX77686 contains three 32.768khz clock outputs that can be controlled
15 The MAX77802 contains two 32.768khz clock outputs that can be controlled
19 The MAX77686 contains one 32.768khz clock outputs that can be controlled
/freebsd/share/man/man4/
H A Dsnd_hdsp.469 (32kHz-48kHz) and 4 channels at double speed (64kHz-96kHz).
70 Only the HDSP 9632 can operate at quad speed (128kHz-192kHz), ADAT is
H A Dsnd_hdspe.468 (32kHz-48kHz), 4 channels at double speed (64kHz-96kHz), and 2 channels at
69 quad speed (128kHz-192kHz).
H A Dsnd_emu10kx.478 PCM support is limited to 48kHz/16 bit stereo (192kHz/24 bit part
83 to 48kHz/16 bit stereo (192kHz/24 bit part of this chipset is not supported).
138 you will get one more DSP device that is rate-locked to 48kHz/16bit/mono.
139 This is actually 48kHz/16bit/32 channels on SB Live! cards and
140 48kHz/16bit/64channels on Audigy cards, but the current implementation of
/freebsd/contrib/file/magic/Magdir/
H A Daudio303 >22 byte =0 replay 5.485 KHz
304 >22 byte =1 replay 8.084 KHz
305 >22 byte =2 replay 10.971 KHz
306 >22 byte =3 replay 16.168 KHz
307 >22 byte =4 replay 21.942 KHz
308 >22 byte =5 replay 32.336 KHz
309 >22 byte =6 replay 43.885 KHz
310 >22 byte =7 replay 47.261 KHz
388 >23 byte 1 33kHz
389 >23 byte 2 50kHz
[all …]
H A Danimation560 >>>2 byte&0x0C 0x00 \b, 44.1 kHz
561 >>>2 byte&0x0C 0x04 \b, 48 kHz
562 >>>2 byte&0x0C 0x08 \b, 32 kHz
595 >2 byte&0x0C 0x00 \b, 44.1 kHz
596 >2 byte&0x0C 0x04 \b, 48 kHz
597 >2 byte&0x0C 0x08 \b, 32 kHz
635 #>>>2 byte&0x0C 0x00 \b, 44.1 kHz
636 #>>>2 byte&0x0C 0x04 \b, 48 kHz
637 #>>>2 byte&0x0C 0x08 \b, 32 kHz
670 >2 byte&0x0C 0x00 \b, 22.05 kHz
[all …]
H A Ddolby13 >4 byte&0xc0 = 0x00 48 kHz,
14 >4 byte&0xc0 = 0x40 44.1 kHz,
15 >4 byte&0xc0 = 0x80 32 kHz,
16 # is this one used for 96 kHz?
/freebsd/sys/contrib/device-tree/src/arm64/renesas/
H A Dr8a779g0-white-hawk-ard-audio-da7212.dtso55 * 44.1kHz groups sound is available by default.
56 * You need to update audio_clkin settings to switch to 48kHz groups sound.
88 /* 44.1kHz groups [(C) clock] */
92 /* 48 kHz groups [(C) clock] */
159 clock-frequency = <5644800>; /* 44.1kHz groups [(C) clock] */
160 // clock-frequency = <6144000>; /* 48 kHz groups [(C) clock] */
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6q-cm-fx6.dts185 /* kHz uV */
192 /* ARM kHz SOC-PU uV */
207 /* kHz uV */
214 /* ARM kHz SOC-PU uV */
229 /* kHz uV */
236 /* ARM kHz SOC-PU uV */
251 /* kHz uV */
258 /* ARM kHz SOC-PU uV */
H A Dimx6q.dtsi25 /* kHz uV */
33 /* ARM kHz SOC-PU uV */
62 /* kHz uV */
70 /* ARM kHz SOC-PU uV */
97 /* kHz uV */
105 /* ARM kHz SOC-PU uV */
132 /* kHz uV */
140 /* ARM kHz SOC-PU uV */
H A Dimx6dl-sabreauto.dts17 /* kHz uV */
23 /* ARM kHz SOC-PU uV */
/freebsd/sys/contrib/device-tree/src/arm/calxeda/
H A Dhighbank.dts29 /* kHz ignored */
48 /* kHz ignored */
67 /* kHz ignored */
86 /* kHz ignored */
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dmax77620.txt36 with internal regulators. 32KHz clock can be programmed to be part of a
46 Each regulator, GPIO1, GPIO2, GPIO3, and 32KHz clock has a flexible power
54 When FPS event cleared (set to LOW), regulators, GPIOs and 32KHz
58 and 32KHz clock get disabled at
68 regulators, GPIOs and 32kHz clocks are provided in their respective
/freebsd/sys/dev/ath/ath_hal/ar5312/
H A Dar5312_misc.c92 * If 32KHz clock exists, use it to lower power consumption during sleep
94 * Note: If clock is set to 32 KHz, delays on accessing certain
115 OS_REG_WRITE(ah, AR_TSF_PARM, 61); /* 32 KHz TSF incr */ in ar5312SetupClock()
139 * If 32KHz clock exists, turn it off and turn back on the 32Mhz
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Drichtek,rt6245-regulator.yaml63 Buck switch frequency selection. Each respective value means 400KHz,
64 800KHz, 1200KHz. If this property is missing then keep in chip default.
/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Di2c-ocores.txt25 Defaults to 100 KHz when the property is not specified
37 frequency is fixed at 100 KHz.
69 clock-frequency = <400000>; /* i2c bus frequency 400 KHz */

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