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Searched +full:k1 +full:- +full:pll (Results 1 – 6 of 6) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dspacemit,k1-pll.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/spacemit,k1-pll.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SpacemiT K1 PLL
10 - Haylen Chu <heylenay@4d2.org>
14 const: spacemit,k1-pll
25 Phandle to the "Main PMU (MPMU)" syscon. It is used to check PLL
28 "#clock-cells":
31 See <dt-bindings/clock/spacemit,k1-syscon.h> for valid indices.
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/freebsd/sys/contrib/device-tree/src/riscv/spacemit/
H A Dk1.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/clock/spacemit,k1-syscon.h>
8 /dts-v1/;
10 #address-cells = <2>;
11 #size-cells = <2>;
12 model = "SpacemiT K1";
13 compatible = "spacemit,k1";
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <24000000>;
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/freebsd/sys/dev/e1000/
H A De1000_ich8lan.h2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
66 #define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */
121 /* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */
132 #define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */
133 #define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */
170 /* Half-duplex collision counts */
188 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
189 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
220 /* Strapping Option Register - RO */
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/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_pll.c1 /*-
38 #include <dt-bindings/clock/tegra124-car.h>
88 /* Post divider <-> register value mapping. */
116 #define PLL(_id, cname, pname) \ macro
123 /* Tegra K1 PLLs
218 PLL(TEGRA124_CLK_PLL_M, "pllM_out0", "osc_div_clk"),
229 PLL(TEGRA124_CLK_PLL_X, "pllX_out", "osc_div_clk"),
242 PLL(TEGRA124_CLK_PLL_C, "pllC_out0", "osc_div_clk"),
255 PLL(TEGRA124_CLK_PLL_C2, "pllC2_out0", "osc_div_clk"),
266 PLL(TEGRA124_CLK_PLL_C3, "pllC3_out0", "osc_div_clk"),
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/freebsd/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h2 * Copyright (c) 2017-2018 Cavium, Inc.
78- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
116 … (0x1<<9) // Fast back-to-back transaction ena…
128 … (0x1<<23) // Fast back-to-back capable. Not ap…
145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
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/freebsd/tests/sys/geom/class/eli/
H A Dtestvect.h1 /* Test Vectors for PBKDF2-SHA512 */
3 …\300!tp\367\257\347c'\000\243F\246\376\274H\263\312m\336\304\3515P\222Cb\037-\313W\0067\232\024%\2…
4 …356?alD\231I[%A\372\367\027\267,\303\022\324\004\302a\302t\257\306S\251\250;-pa\246Z\200\003*+\026…
10 …4\334\005O,\374\225\234\014\266\365\030i6\210a\205", 100, "\220\006\216\2420-8m\2766\353(6\212\306…
16 …00, "\334\222G\300~'\042LS\0218\006,\261\207]\277\245GH\007\246\357f\205\325-\3044\337\347\007\373…
17 …212\377\257\177\350f\276\330\3035\204\215\327f\256\300\364\212\271\306q\242?-\307\324\317y^\201t\2…
18 …{ "\234^\035\320rt-B", 8, "\357\274\204\366N9\273:\216\331,D\300t\320\361\324F\313\220E\250u\203\3…
25 …5\317 w\034u?", 300, "\276\317.\310Gj \217\3502.za\021\230\322C6\255\301\354-\263\247\002\352\377\…
26 …{ "\265G\357\330S\302?8", 8, "7S-\203\036\340\015\356\027\253\302\376\222\037\2276\0141|p\255\313\…
32 …{ "p(\256-\313\020{\300", 8, "\334\310\227\225J\356\360\307!\353\023\332|\214\306\036\026\253|-\26…
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