18cfa0ad2SJack F Vogel /****************************************************************************** 27282444bSPedro F. Giffuni SPDX-License-Identifier: BSD-3-Clause 38cfa0ad2SJack F Vogel 4702cac6cSKevin Bowling Copyright (c) 2001-2020, Intel Corporation 58cfa0ad2SJack F Vogel All rights reserved. 68cfa0ad2SJack F Vogel 78cfa0ad2SJack F Vogel Redistribution and use in source and binary forms, with or without 88cfa0ad2SJack F Vogel modification, are permitted provided that the following conditions are met: 98cfa0ad2SJack F Vogel 108cfa0ad2SJack F Vogel 1. Redistributions of source code must retain the above copyright notice, 118cfa0ad2SJack F Vogel this list of conditions and the following disclaimer. 128cfa0ad2SJack F Vogel 138cfa0ad2SJack F Vogel 2. Redistributions in binary form must reproduce the above copyright 148cfa0ad2SJack F Vogel notice, this list of conditions and the following disclaimer in the 158cfa0ad2SJack F Vogel documentation and/or other materials provided with the distribution. 168cfa0ad2SJack F Vogel 178cfa0ad2SJack F Vogel 3. Neither the name of the Intel Corporation nor the names of its 188cfa0ad2SJack F Vogel contributors may be used to endorse or promote products derived from 198cfa0ad2SJack F Vogel this software without specific prior written permission. 208cfa0ad2SJack F Vogel 218cfa0ad2SJack F Vogel THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 228cfa0ad2SJack F Vogel AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 238cfa0ad2SJack F Vogel IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 248cfa0ad2SJack F Vogel ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 258cfa0ad2SJack F Vogel LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 268cfa0ad2SJack F Vogel CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 278cfa0ad2SJack F Vogel SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 288cfa0ad2SJack F Vogel INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 298cfa0ad2SJack F Vogel CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 308cfa0ad2SJack F Vogel ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 318cfa0ad2SJack F Vogel POSSIBILITY OF SUCH DAMAGE. 328cfa0ad2SJack F Vogel 338cfa0ad2SJack F Vogel ******************************************************************************/ 348cfa0ad2SJack F Vogel 358cfa0ad2SJack F Vogel #ifndef _E1000_ICH8LAN_H_ 368cfa0ad2SJack F Vogel #define _E1000_ICH8LAN_H_ 378cfa0ad2SJack F Vogel 38c597a019SSean Bruno #define ICH_FLASH_GFPREG 0x0000 39c597a019SSean Bruno #define ICH_FLASH_HSFSTS 0x0004 40c597a019SSean Bruno #define ICH_FLASH_HSFCTL 0x0006 41c597a019SSean Bruno #define ICH_FLASH_FADDR 0x0008 42c597a019SSean Bruno #define ICH_FLASH_FDATA0 0x0010 438cfa0ad2SJack F Vogel 44d035aa2dSJack F Vogel /* Requires up to 10 seconds when MNG might be accessing part. */ 45d035aa2dSJack F Vogel #define ICH_FLASH_READ_COMMAND_TIMEOUT 10000000 46d035aa2dSJack F Vogel #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 10000000 47d035aa2dSJack F Vogel #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 10000000 488cfa0ad2SJack F Vogel #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF 498cfa0ad2SJack F Vogel #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 508cfa0ad2SJack F Vogel 518cfa0ad2SJack F Vogel #define ICH_CYCLE_READ 0 528cfa0ad2SJack F Vogel #define ICH_CYCLE_WRITE 2 538cfa0ad2SJack F Vogel #define ICH_CYCLE_ERASE 3 548cfa0ad2SJack F Vogel 558cfa0ad2SJack F Vogel #define FLASH_GFPREG_BASE_MASK 0x1FFF 568cfa0ad2SJack F Vogel #define FLASH_SECTOR_ADDR_SHIFT 12 578cfa0ad2SJack F Vogel 588cfa0ad2SJack F Vogel #define ICH_FLASH_SEG_SIZE_256 256 598cfa0ad2SJack F Vogel #define ICH_FLASH_SEG_SIZE_4K 4096 608cfa0ad2SJack F Vogel #define ICH_FLASH_SEG_SIZE_8K 8192 618cfa0ad2SJack F Vogel #define ICH_FLASH_SEG_SIZE_64K 65536 628cfa0ad2SJack F Vogel 638cfa0ad2SJack F Vogel #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ 648cfa0ad2SJack F Vogel /* FW established a valid mode */ 658cfa0ad2SJack F Vogel #define E1000_ICH_FWSM_FW_VALID 0x00008000 664dab5c37SJack F Vogel #define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */ 674dab5c37SJack F Vogel #define E1000_ICH_FWSM_PCIM2PCI_COUNT 2000 688cfa0ad2SJack F Vogel 698cfa0ad2SJack F Vogel #define E1000_ICH_MNG_IAMT_MODE 0x2 708cfa0ad2SJack F Vogel 716ab6bfe3SJack F Vogel #define E1000_FWSM_WLOCK_MAC_MASK 0x0380 726ab6bfe3SJack F Vogel #define E1000_FWSM_WLOCK_MAC_SHIFT 7 738cc64f1eSJack F Vogel #define E1000_FWSM_ULP_CFG_DONE 0x00000400 /* Low power cfg done */ 747d9119bdSJack F Vogel 757d9119bdSJack F Vogel /* Shared Receive Address Registers */ 766ab6bfe3SJack F Vogel #define E1000_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8)) 776ab6bfe3SJack F Vogel #define E1000_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8)) 787d9119bdSJack F Vogel 798cc64f1eSJack F Vogel #define E1000_H2ME 0x05B50 /* Host to ME */ 808cc64f1eSJack F Vogel #define E1000_H2ME_ULP 0x00000800 /* ULP Indication Bit */ 818cc64f1eSJack F Vogel #define E1000_H2ME_ENFORCE_SETTINGS 0x00001000 /* Enforce Settings */ 828cc64f1eSJack F Vogel 838cfa0ad2SJack F Vogel #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ 84d035aa2dSJack F Vogel (ID_LED_OFF1_OFF2 << 8) | \ 85d035aa2dSJack F Vogel (ID_LED_OFF1_ON2 << 4) | \ 868cfa0ad2SJack F Vogel (ID_LED_DEF1_DEF2)) 878cfa0ad2SJack F Vogel 888cfa0ad2SJack F Vogel #define E1000_ICH_NVM_SIG_WORD 0x13 898cfa0ad2SJack F Vogel #define E1000_ICH_NVM_SIG_MASK 0xC000 90d035aa2dSJack F Vogel #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0 91d035aa2dSJack F Vogel #define E1000_ICH_NVM_SIG_VALUE 0x80 928cfa0ad2SJack F Vogel 938cfa0ad2SJack F Vogel #define E1000_ICH8_LAN_INIT_TIMEOUT 1500 948cfa0ad2SJack F Vogel 958cc64f1eSJack F Vogel /* FEXT register bit definition */ 968cc64f1eSJack F Vogel #define E1000_FEXT_PHY_CABLE_DISCONNECTED 0x00000004 978cc64f1eSJack F Vogel 988cfa0ad2SJack F Vogel #define E1000_FEXTNVM_SW_CONFIG 1 997609433eSJack F Vogel #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* different on ICH8M */ 1008cfa0ad2SJack F Vogel 1016ab6bfe3SJack F Vogel #define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK 0x0C000000 1026ab6bfe3SJack F Vogel #define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC 0x08000000 1036ab6bfe3SJack F Vogel 1047d9119bdSJack F Vogel #define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7 1057d9119bdSJack F Vogel #define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7 1067d9119bdSJack F Vogel #define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3 1077d9119bdSJack F Vogel 1086ab6bfe3SJack F Vogel #define E1000_FEXTNVM6_REQ_PLL_CLK 0x00000100 1097609433eSJack F Vogel #define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION 0x00000200 110c80429ceSEric Joyner #define E1000_FEXTNVM6_K1_OFF_ENABLE 0x80000000 111c80429ceSEric Joyner /* bit for disabling packet buffer read */ 112c80429ceSEric Joyner #define E1000_FEXTNVM7_DISABLE_PB_READ 0x00040000 113c80429ceSEric Joyner #define E1000_FEXTNVM7_SIDE_CLK_UNGATE 0x00000004 1148cc64f1eSJack F Vogel #define E1000_FEXTNVM7_DISABLE_SMB_PERST 0x00000020 115de965d04SGuinan Sun #define E1000_FEXTNVM8_UNBIND_DPG_FROM_MPHY 0x00000400 116c80429ceSEric Joyner #define E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS 0x00000800 117c80429ceSEric Joyner #define E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS 0x00001000 118c80429ceSEric Joyner #define E1000_FEXTNVM11_DISABLE_PB_READ 0x00000200 119c80429ceSEric Joyner #define E1000_FEXTNVM11_DISABLE_MULR_FIX 0x00002000 120de965d04SGuinan Sun #define E1000_FEXTNVM12_DONT_WAK_DPG_CLKREQ 0x00001000 121c80429ceSEric Joyner /* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */ 122c80429ceSEric Joyner #define E1000_RXDCTL_THRESH_UNIT_DESC 0x01000000 123c80429ceSEric Joyner 124c80429ceSEric Joyner #define NVM_SIZE_MULTIPLIER 4096 /*multiplier for NVMS field*/ 125c80429ceSEric Joyner #define E1000_FLASH_BASE_ADDR 0xE000 /*offset of NVM access regs*/ 126c80429ceSEric Joyner #define E1000_CTRL_EXT_NVMVS 0x3 /*NVM valid sector */ 1276fe4c0a0SSean Bruno #define E1000_TARC0_CB_MULTIQ_3_REQ 0x30000000 1286fe4c0a0SSean Bruno #define E1000_TARC0_CB_MULTIQ_2_REQ 0x20000000 1298cfa0ad2SJack F Vogel #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL 1308cfa0ad2SJack F Vogel 1318cfa0ad2SJack F Vogel #define E1000_ICH_RAR_ENTRIES 7 1328cc64f1eSJack F Vogel #define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */ 1336ab6bfe3SJack F Vogel #define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */ 1348cfa0ad2SJack F Vogel 1358cfa0ad2SJack F Vogel #define PHY_PAGE_SHIFT 5 1368cfa0ad2SJack F Vogel #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ 1378cfa0ad2SJack F Vogel ((reg) & MAX_PHY_REG_ADDRESS)) 1388cfa0ad2SJack F Vogel #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */ 1398cfa0ad2SJack F Vogel #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */ 1408cfa0ad2SJack F Vogel 1418cfa0ad2SJack F Vogel #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 1428cfa0ad2SJack F Vogel #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 1438cfa0ad2SJack F Vogel #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 1448cfa0ad2SJack F Vogel 145d035aa2dSJack F Vogel /* PHY Wakeup Registers and defines */ 1464dab5c37SJack F Vogel #define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17) 147d035aa2dSJack F Vogel #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0) 148d035aa2dSJack F Vogel #define BM_WUC PHY_REG(BM_WUC_PAGE, 1) 149d035aa2dSJack F Vogel #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2) 150d035aa2dSJack F Vogel #define BM_WUS PHY_REG(BM_WUC_PAGE, 3) 151d035aa2dSJack F Vogel #define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2))) 152d035aa2dSJack F Vogel #define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2))) 153d035aa2dSJack F Vogel #define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2))) 154d035aa2dSJack F Vogel #define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2))) 155d035aa2dSJack F Vogel #define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1))) 156d035aa2dSJack F Vogel 157d035aa2dSJack F Vogel #define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */ 158d035aa2dSJack F Vogel #define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */ 159d035aa2dSJack F Vogel #define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */ 160d035aa2dSJack F Vogel #define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */ 161d035aa2dSJack F Vogel #define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */ 162d035aa2dSJack F Vogel #define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */ 163d035aa2dSJack F Vogel #define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */ 164d035aa2dSJack F Vogel 1659d81738fSJack F Vogel #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */ 1669d81738fSJack F Vogel #define HV_MUX_DATA_CTRL PHY_REG(776, 16) 1679d81738fSJack F Vogel #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400 1689d81738fSJack F Vogel #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004 1694dab5c37SJack F Vogel #define HV_STATS_PAGE 778 1707609433eSJack F Vogel /* Half-duplex collision counts */ 1717609433eSJack F Vogel #define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision */ 1724dab5c37SJack F Vogel #define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17) 1737609433eSJack F Vogel #define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. */ 1744dab5c37SJack F Vogel #define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19) 1757609433eSJack F Vogel #define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Collision */ 1764dab5c37SJack F Vogel #define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21) 1777609433eSJack F Vogel #define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision */ 1784dab5c37SJack F Vogel #define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24) 1797609433eSJack F Vogel #define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision */ 1804dab5c37SJack F Vogel #define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26) 1814dab5c37SJack F Vogel #define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */ 1824dab5c37SJack F Vogel #define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28) 1837609433eSJack F Vogel #define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Tx with no CRS */ 1844dab5c37SJack F Vogel #define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30) 1859d81738fSJack F Vogel 1864edd8523SJack F Vogel #define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */ 1874edd8523SJack F Vogel 1884edd8523SJack F Vogel #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */ 1894edd8523SJack F Vogel #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */ 190c80429ceSEric Joyner #define K1_ENTRY_LATENCY 0 191c80429ceSEric Joyner #define K1_MIN_TIME 1 1924edd8523SJack F Vogel 1936ab6bfe3SJack F Vogel /* SMBus Control Phy Register */ 1946ab6bfe3SJack F Vogel #define CV_SMB_CTRL PHY_REG(769, 23) 1956ab6bfe3SJack F Vogel #define CV_SMB_CTRL_FORCE_SMBUS 0x0001 1966ab6bfe3SJack F Vogel 1978cc64f1eSJack F Vogel /* I218 Ultra Low Power Configuration 1 Register */ 1988cc64f1eSJack F Vogel #define I218_ULP_CONFIG1 PHY_REG(779, 16) 1998cc64f1eSJack F Vogel #define I218_ULP_CONFIG1_START 0x0001 /* Start auto ULP config */ 2008cc64f1eSJack F Vogel #define I218_ULP_CONFIG1_IND 0x0004 /* Pwr up from ULP indication */ 2018cc64f1eSJack F Vogel #define I218_ULP_CONFIG1_STICKY_ULP 0x0010 /* Set sticky ULP mode */ 2028cc64f1eSJack F Vogel #define I218_ULP_CONFIG1_INBAND_EXIT 0x0020 /* Inband on ULP exit */ 2038cc64f1eSJack F Vogel #define I218_ULP_CONFIG1_WOL_HOST 0x0040 /* WoL Host on ULP exit */ 2048cc64f1eSJack F Vogel #define I218_ULP_CONFIG1_RESET_TO_SMBUS 0x0100 /* Reset to SMBus mode */ 205c80429ceSEric Joyner /* enable ULP even if when phy powered down via lanphypc */ 206c80429ceSEric Joyner #define I218_ULP_CONFIG1_EN_ULP_LANPHYPC 0x0400 207c80429ceSEric Joyner /* disable clear of sticky ULP on PERST */ 208c80429ceSEric Joyner #define I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST 0x0800 2098cc64f1eSJack F Vogel #define I218_ULP_CONFIG1_DISABLE_SMB_PERST 0x1000 /* Disable on PERST# */ 2108cc64f1eSJack F Vogel 2114edd8523SJack F Vogel /* SMBus Address Phy Register */ 2124edd8523SJack F Vogel #define HV_SMB_ADDR PHY_REG(768, 26) 2137d9119bdSJack F Vogel #define HV_SMB_ADDR_MASK 0x007F 2144edd8523SJack F Vogel #define HV_SMB_ADDR_PEC_EN 0x0200 2154edd8523SJack F Vogel #define HV_SMB_ADDR_VALID 0x0080 2166ab6bfe3SJack F Vogel #define HV_SMB_ADDR_FREQ_MASK 0x1100 2176ab6bfe3SJack F Vogel #define HV_SMB_ADDR_FREQ_LOW_SHIFT 8 2186ab6bfe3SJack F Vogel #define HV_SMB_ADDR_FREQ_HIGH_SHIFT 12 2194edd8523SJack F Vogel 2204edd8523SJack F Vogel /* Strapping Option Register - RO */ 2214edd8523SJack F Vogel #define E1000_STRAP 0x0000C 2224edd8523SJack F Vogel #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000 2234edd8523SJack F Vogel #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17 2246ab6bfe3SJack F Vogel #define E1000_STRAP_SMT_FREQ_MASK 0x00003000 2256ab6bfe3SJack F Vogel #define E1000_STRAP_SMT_FREQ_SHIFT 12 2264edd8523SJack F Vogel 2274edd8523SJack F Vogel /* OEM Bits Phy Register */ 2284edd8523SJack F Vogel #define HV_OEM_BITS PHY_REG(768, 25) 2294edd8523SJack F Vogel #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */ 2304edd8523SJack F Vogel #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */ 2314edd8523SJack F Vogel #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */ 2324edd8523SJack F Vogel 233a69ed8dfSJack F Vogel /* KMRN Mode Control */ 234a69ed8dfSJack F Vogel #define HV_KMRN_MODE_CTRL PHY_REG(769, 16) 235a69ed8dfSJack F Vogel #define HV_KMRN_MDIO_SLOW 0x0400 236a69ed8dfSJack F Vogel 2374dab5c37SJack F Vogel /* KMRN FIFO Control and Status */ 2384dab5c37SJack F Vogel #define HV_KMRN_FIFO_CTRLSTA PHY_REG(770, 16) 2394dab5c37SJack F Vogel #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000 2404dab5c37SJack F Vogel #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT 12 2414dab5c37SJack F Vogel 2428ec87fc5SJack F Vogel /* PHY Power Management Control */ 2438ec87fc5SJack F Vogel #define HV_PM_CTRL PHY_REG(770, 17) 244e760e292SSean Bruno #define HV_PM_CTRL_K1_CLK_REQ 0x200 2458cc64f1eSJack F Vogel #define HV_PM_CTRL_K1_ENABLE 0x4000 2468ec87fc5SJack F Vogel 247c80429ceSEric Joyner #define I217_PLL_CLOCK_GATE_REG PHY_REG(772, 28) 248c80429ceSEric Joyner #define I217_PLL_CLOCK_GATE_MASK 0x07FF 249c80429ceSEric Joyner 2504dab5c37SJack F Vogel #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in ms */ 2514edd8523SJack F Vogel 2527609433eSJack F Vogel /* Inband Control */ 2537609433eSJack F Vogel #define I217_INBAND_CTRL PHY_REG(770, 18) 2547609433eSJack F Vogel #define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK 0x3F00 2557609433eSJack F Vogel #define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT 8 2567609433eSJack F Vogel 2577609433eSJack F Vogel /* Low Power Idle GPIO Control */ 2587609433eSJack F Vogel #define I217_LPI_GPIO_CTRL PHY_REG(772, 18) 2597609433eSJack F Vogel #define I217_LPI_GPIO_CTRL_AUTO_EN_LPI 0x0800 2607609433eSJack F Vogel 2617d9119bdSJack F Vogel /* PHY Low Power Idle Control */ 2627d9119bdSJack F Vogel #define I82579_LPI_CTRL PHY_REG(772, 20) 2636ab6bfe3SJack F Vogel #define I82579_LPI_CTRL_100_ENABLE 0x2000 2646ab6bfe3SJack F Vogel #define I82579_LPI_CTRL_1000_ENABLE 0x4000 2657d9119bdSJack F Vogel #define I82579_LPI_CTRL_ENABLE_MASK 0x6000 2667d9119bdSJack F Vogel 2677609433eSJack F Vogel /* 82579 DFT Control */ 2687609433eSJack F Vogel #define I82579_DFT_CTRL PHY_REG(769, 20) 2697609433eSJack F Vogel #define I82579_DFT_CTRL_GATE_PHY_RESET 0x0040 /* Gate PHY Reset on MAC Reset */ 2707609433eSJack F Vogel 2716ab6bfe3SJack F Vogel /* Extended Management Interface (EMI) Registers */ 272730d3130SJack F Vogel #define I82579_EMI_ADDR 0x10 273730d3130SJack F Vogel #define I82579_EMI_DATA 0x11 274730d3130SJack F Vogel #define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */ 2756ab6bfe3SJack F Vogel #define I82579_MSE_THRESHOLD 0x084F /* 82579 Mean Square Error Threshold */ 2766ab6bfe3SJack F Vogel #define I82577_MSE_THRESHOLD 0x0887 /* 82577 Mean Square Error Threshold */ 2774dab5c37SJack F Vogel #define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */ 2786ab6bfe3SJack F Vogel #define I82579_RX_CONFIG 0x3412 /* Receive configuration */ 2798cc64f1eSJack F Vogel #define I82579_LPI_PLL_SHUT 0x4412 /* LPI PLL Shut Enable */ 2807609433eSJack F Vogel #define I82579_EEE_PCS_STATUS 0x182E /* IEEE MMD Register 3.1 >> 8 */ 2816ab6bfe3SJack F Vogel #define I82579_EEE_CAPABILITY 0x0410 /* IEEE MMD Register 3.20 */ 2826ab6bfe3SJack F Vogel #define I82579_EEE_ADVERTISEMENT 0x040E /* IEEE MMD Register 7.60 */ 2836ab6bfe3SJack F Vogel #define I82579_EEE_LP_ABILITY 0x040F /* IEEE MMD Register 7.61 */ 2847609433eSJack F Vogel #define I82579_EEE_100_SUPPORTED (1 << 1) /* 100BaseTx EEE */ 2857609433eSJack F Vogel #define I82579_EEE_1000_SUPPORTED (1 << 2) /* 1000BaseTx EEE */ 2868cc64f1eSJack F Vogel #define I82579_LPI_100_PLL_SHUT (1 << 2) /* 100M LPI PLL Shut Enabled */ 2876ab6bfe3SJack F Vogel #define I217_EEE_PCS_STATUS 0x9401 /* IEEE MMD Register 3.1 */ 2886ab6bfe3SJack F Vogel #define I217_EEE_CAPABILITY 0x8000 /* IEEE MMD Register 3.20 */ 2896ab6bfe3SJack F Vogel #define I217_EEE_ADVERTISEMENT 0x8001 /* IEEE MMD Register 7.60 */ 2906ab6bfe3SJack F Vogel #define I217_EEE_LP_ABILITY 0x8002 /* IEEE MMD Register 7.61 */ 2918cc64f1eSJack F Vogel #define I217_RX_CONFIG 0xB20C /* Receive configuration */ 292730d3130SJack F Vogel 2936ab6bfe3SJack F Vogel #define E1000_EEE_RX_LPI_RCVD 0x0400 /* Tx LP idle received */ 2946ab6bfe3SJack F Vogel #define E1000_EEE_TX_LPI_RCVD 0x0800 /* Rx LP idle received */ 2958cfa0ad2SJack F Vogel 2966ab6bfe3SJack F Vogel /* Intel Rapid Start Technology Support */ 2976ab6bfe3SJack F Vogel #define I217_PROXY_CTRL BM_PHY_REG(BM_WUC_PAGE, 70) 2986ab6bfe3SJack F Vogel #define I217_PROXY_CTRL_AUTO_DISABLE 0x0080 2996ab6bfe3SJack F Vogel #define I217_SxCTRL PHY_REG(BM_PORT_CTRL_PAGE, 28) 3006ab6bfe3SJack F Vogel #define I217_SxCTRL_ENABLE_LPI_RESET 0x1000 3016ab6bfe3SJack F Vogel #define I217_CGFREG PHY_REG(772, 29) 3026ab6bfe3SJack F Vogel #define I217_CGFREG_ENABLE_MTA_RESET 0x0002 3036ab6bfe3SJack F Vogel #define I217_MEMPWR PHY_REG(772, 26) 3046ab6bfe3SJack F Vogel #define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010 3058cfa0ad2SJack F Vogel 3067d9119bdSJack F Vogel /* Receive Address Initial CRC Calculation */ 3077d9119bdSJack F Vogel #define E1000_PCH_RAICC(_n) (0x05F50 + ((_n) * 4)) 3087d9119bdSJack F Vogel 309e373323fSSean Bruno /* Latency Tolerance Reporting */ 310e373323fSSean Bruno #define E1000_LTRV 0x000F8 311e373323fSSean Bruno #define E1000_LTRV_VALUE_MASK 0x000003FF 312e373323fSSean Bruno #define E1000_LTRV_SCALE_MAX 5 313e373323fSSean Bruno #define E1000_LTRV_SCALE_FACTOR 5 314e373323fSSean Bruno #define E1000_LTRV_SCALE_SHIFT 10 315e373323fSSean Bruno #define E1000_LTRV_SCALE_MASK 0x00001C00 316e373323fSSean Bruno #define E1000_LTRV_REQ_SHIFT 15 317e373323fSSean Bruno #define E1000_LTRV_NOSNOOP_SHIFT 16 318e373323fSSean Bruno #define E1000_LTRV_SEND (1 << 30) 319e373323fSSean Bruno 320e373323fSSean Bruno /* Proprietary Latency Tolerance Reporting PCI Capability */ 321e373323fSSean Bruno #define E1000_PCI_LTR_CAP_LPT 0xA8 322e373323fSSean Bruno 323e373323fSSean Bruno /* OBFF Control & Threshold Defines */ 324e373323fSSean Bruno #define E1000_SVCR_OFF_EN 0x00000001 325e373323fSSean Bruno #define E1000_SVCR_OFF_MASKINT 0x00001000 326e373323fSSean Bruno #define E1000_SVCR_OFF_TIMER_MASK 0xFFFF0000 327e373323fSSean Bruno #define E1000_SVCR_OFF_TIMER_SHIFT 16 328e373323fSSean Bruno #define E1000_SVT_OFF_HWM_MASK 0x0000001F 329e373323fSSean Bruno 330d50f362bSGuinan Sun #define E1000_PCI_VENDOR_ID_REGISTER 0x00 331d50f362bSGuinan Sun 3328cfa0ad2SJack F Vogel void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 3338cfa0ad2SJack F Vogel bool state); 3348cfa0ad2SJack F Vogel void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); 3358cfa0ad2SJack F Vogel void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw); 3364dab5c37SJack F Vogel void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw); 337c80429ceSEric Joyner u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw); 3384edd8523SJack F Vogel s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable); 339*d5ad2f2aSWenzhuo Lu s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time); 3407d9119bdSJack F Vogel void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw); 3417d9119bdSJack F Vogel s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable); 3426ab6bfe3SJack F Vogel s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data); 3437609433eSJack F Vogel s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data); 3447609433eSJack F Vogel s32 e1000_set_eee_pchlan(struct e1000_hw *hw); 3458cc64f1eSJack F Vogel s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx); 3468cc64f1eSJack F Vogel s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force); 3476ab6bfe3SJack F Vogel #endif /* _E1000_ICH8LAN_H_ */ 348