Home
last modified time | relevance | path

Searched +full:jh7110 +full:- +full:pmu (Results 1 – 6 of 6) sorted by relevance

/linux/Documentation/devicetree/bindings/power/
H A Dstarfive,jh7110-pmu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/starfive,jh7110-pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 Power Management Unit
10 - Walker Chen <walker.chen@starfivetech.com>
13 StarFive JH7110 SoC includes support for multiple power domains which can be
19 - starfive,jh7110-pmu
27 "#power-domain-cells":
31 - compatible
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dstarfive,jh7110-voutcrg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-voutcrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 Video-Output Clock and Reset Generator
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
14 const: starfive,jh7110-voutcrg
21 - description: Vout Top core
22 - description: Vout Top Ahb
23 - description: Vout Top Axi
[all …]
H A Dstarfive,jh7110-ispcrg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
14 const: starfive,jh7110-ispcrg
21 - description: ISP Top core
22 - description: ISP Top Axi
23 - description: NOC ISP Bus
[all …]
/linux/drivers/pmdomain/starfive/
H A Djh71xx-pmu.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * StarFive JH71XX PMU (Power Management Unit) Controller Driver
5 * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
15 #include <dt-bindings/power/starfive,jh7110-pmu.h>
26 /* aon pmu register offset */
36 /* pmu int status */
64 struct jh71xx_pmu *pmu);
76 spinlock_t lock; /* protects pmu reg */
81 struct jh71xx_pmu *pmu; member
87 struct jh71xx_pmu *pmu = pmd->pmu; in jh71xx_pmu_get_state() local
[all …]
/linux/arch/riscv/
H A DKconfig.errata20 non-standard handling on non-coherent operations on Andes cores.
58 bool "Apply SiFive errata CIP-453"
62 This will apply the SiFive CIP-453 errata to add sign extension
69 bool "Apply SiFive errata CIP-1200"
73 This will apply the SiFive CIP-1200 errata to repalce all
90 The StarFive JH7100 was a test chip for the JH7110 and has
91 caches that are non-coherent with respect to peripheral DMAs.
92 It was designed before the Zicbom extension so needs non-standard
99 bool "T-HEAD errata"
102 All T-HEAD errata Kconfig depend on this Kconfig. Disabling
[all …]
/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
[all …]