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Searched +full:irq +full:- +full:syscfg (Results 1 – 22 of 22) sorted by relevance

/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dst,stih407-irq-syscfg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/st,stih407-irq-syscfg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Patrice Chotard <patrice.chotard@foss.st.com>
19 const: st,stih407-irq-syscfg
21 st,syscfg:
22 description: Phandle to Cortex-A9 IRQ system config registers
25 st,irq-device:
27 $ref: /schemas/types.yaml#/definitions/uint32-array
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/linux/drivers/irqchip/
H A Dirq-st.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * This is a re-write of Christophe Kerello's PMU driver.
10 #include <dt-bindings/interrupt-controller/irq-st.h>
38 unsigned int syscfg; member
45 .compatible = "st,stih407-irq-syscfg",
52 int device, int channel, bool irq) in st_irq_xlate() argument
54 struct st_irq_syscfg *ddata = dev_get_drvdata(&pdev->dev); in st_irq_xlate()
59 ddata->config |= ST_A9_IRQ_EN_EXT_0; in st_irq_xlate()
62 ddata->config |= ST_A9_IRQ_EN_EXT_1; in st_irq_xlate()
65 ddata->config |= ST_A9_IRQ_EN_EXT_2; in st_irq_xlate()
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/linux/drivers/phy/st/
H A Dphy-stm32-combophy.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <dt-bindings/phy/phy.h>
26 /* SYSCFG PCIEPRGCR */
31 /* SYSCFG SYSCFG_COMBOPHY_SR */
34 /* SYSCFG CR1 */
42 /* SYSCFG CR4 */
61 /* SYSCFG CR2 */
68 /* SYSCFG CR5 */
122 u32 min_imp = imp_lookup[imp_size - 1].microohm; in stm32_impedance_tune()
127 if (!of_property_read_u32(combophy->dev->of_node, "st,output-micro-ohms", &val)) { in stm32_impedance_tune()
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dpinctrl-st.txt3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
14 GPIO bank can have one of the two possible types of interrupt-wirings.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
28 [irqN]----> [gpio-bank (n)]
33 - compatible : should be "st,stih407-<pio-block>-pinctrl"
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H A Dst,stm32-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre TORGUE <alexandre.torgue@foss.st.com>
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
25 - st,stm32f769-pinctrl
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/linux/Documentation/devicetree/bindings/iio/adc/
H A Dst,stm32-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 STM32 ADC is a successive approximation analog-to-digital converter.
13 stored in a left-aligned or right-aligned 32-bit data register.
17 voltage goes beyond the user-defined, higher or lower thresholds.
22 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
27 - st,stm32f4-adc-core
28 - st,stm32h7-adc-core
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/linux/drivers/pci/controller/dwc/
H A Dpcie-stm32-ep.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include "pcie-designware.h"
19 #include "pcie-stm32.h"
44 regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, in stm32_pcie_enable_link()
55 regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, STM32MP25_PCIECR_LTSSM_EN, 0); in stm32_pcie_disable_link()
63 dev_dbg(pci->dev, "Enable link\n"); in stm32_pcie_start_link()
67 dev_err(pci->dev, "PCIe cannot establish link: %d\n", ret); in stm32_pcie_start_link()
71 enable_irq(stm32_pcie->perst_irq); in stm32_pcie_start_link()
80 dev_dbg(pci->dev, "Disable link\n"); in stm32_pcie_stop_link()
82 disable_irq(stm32_pcie->perst_irq); in stm32_pcie_stop_link()
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H A Dpcie-stm32.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include "pcie-designware.h"
20 #include "pcie-stm32.h"
35 if (stm32_pcie->perst_gpio) { in stm32_pcie_deassert_perst()
37 gpiod_set_value(stm32_pcie->perst_gpio, 0); in stm32_pcie_deassert_perst()
45 gpiod_set_value(stm32_pcie->perst_gpio, 1); in stm32_pcie_assert_perst()
52 return regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, in stm32_pcie_start_link()
61 regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, in stm32_pcie_stop_link()
70 ret = dw_pcie_suspend_noirq(&stm32_pcie->pci); in stm32_pcie_suspend_noirq()
76 clk_disable_unprepare(stm32_pcie->clk); in stm32_pcie_suspend_noirq()
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/linux/drivers/usb/renesas_usbhs/
H A Dcommon.h1 /* SPDX-License-Identifier: GPL-1.0+ */
28 #define SYSCFG 0x0000 macro
100 #define D2FIFOSEL 0x00F0 /* for R-Car Gen2 */
101 #define D2FIFOCTR 0x00F2 /* for R-Car Gen2 */
102 #define D3FIFOSEL 0x00F4 /* for R-Car Gen2 */
103 #define D3FIFOCTR 0x00F6 /* for R-Car Gen2 */
106 /* SYSCFG */
108 #define CNEN (1 << 8) /* Single-ended receiver operation Enable */
109 #define HSE (1 << 7) /* High-Speed Operation Enable */
111 #define DRPD (1 << 5) /* D+ Line/D- Line Resistance Control */
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/linux/arch/arm/boot/dts/st/
H A Dstm32h743.dtsi2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include "../armv7-m.dtsi"
44 #include <dt-bindings/clock/stm32h7-clks.h>
45 #include <dt-bindings/mfd/stm32h7-rcc.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
49 #address-cells = <1>;
50 #size-cells = <1>;
53 clk_hse: clk-hse {
54 #clock-cells = <0>;
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H A Dstm32f746.dtsi2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include "../armv7-m.dtsi"
44 #include <dt-bindings/clock/stm32fx-clock.h>
45 #include <dt-bindings/mfd/stm32f7-rcc.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
49 #address-cells = <1>;
50 #size-cells = <1>;
53 clk_hse: clk-hse {
54 #clock-cells = <0>;
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/linux/arch/arm/boot/dts/mediatek/
H A Dmt8135.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt8135-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/mt8135-resets.h>
12 #include <dt-bindings/pinctrl/mt8135-pinfunc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
18 interrupt-parent = <&sysirq>;
20 cpu-map {
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H A Dmt2701.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt2701-clk.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/mt2701-power.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/memory/mt2701-larb-port.h>
14 #include <dt-bindings/reset/mt2701-resets.h>
15 #include "mt2701-pinfunc.h"
18 #address-cells = <2>;
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/linux/Documentation/devicetree/bindings/misc/
H A Dpci1de4,1.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - A. della Porta <andrea.porta@suse.com>
19 - $ref: /schemas/pci/pci-ep-bus.yaml
26 - const: pci1de4,1
28 '#interrupt-cells':
32 in include/dt-bindings/interrupt-controller/irq.h.
36 - IO BANK0: 0
37 - IO BANK1: 1
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/linux/Documentation/devicetree/bindings/display/
H A Dst,stih4xx.txt3 - sti-vtg: video timing generator
5 - compatible: "st,vtg"
6 - reg: Physical base address of the IP registers and length of memory mapped region.
8 - interrupts : VTG interrupt number to the CPU.
9 - st,slave: phandle on a slave vtg
11 - sti-vtac: video timing advanced inter dye communication Rx and TX
13 - compatible: "st,vtac-main" or "st,vtac-aux"
14 - reg: Physical base address of the IP registers and length of memory mapped region.
15 - clocks: from common clock binding: handle hardware IP needed clocks, the
17 See ../clocks/clock-bindings.txt for details.
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/linux/drivers/ata/
H A Dsata_sil.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sata_sil.c - Silicon Image SATA
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2005 Red Hat, Inc.
13 * as Documentation/driver-api/libata.rst
16 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
65 /* SYSCFG */
78 SIL_DMA_RDWR = (1 << 3), /* DMA Rd-Wr */
82 SIL_DMA_COMPLETE = (1 << 18), /* cmd complete / IRQ pending */
127 /* TODO firmware versions should be added - eric */
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/linux/drivers/pinctrl/
H A Dpinctrl-st.c1 // SPDX-License-Identifier: GPL-2.0-only
100 * (direction, retime-type, retime-clk, retime-delay)
102 * +----------------+
103 *[31:28]| reserved-3 |
104 * +----------------+-------------
106 * +----------------+ v
108 * +----------------+ ^
110 * +----------------+-------------
111 *[24] | reserved-2 |
112 * +----------------+-------------
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/linux/drivers/rtc/
H A Drtc-stm32.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
18 #include <linux/pinctrl/pinconf-generic.h>
189 const struct stm32_rtc_registers *regs = &rtc->data->regs; in stm32_rtc_wpr_unlock()
191 writel_relaxed(RTC_WPR_1ST_KEY, rtc->base + regs->wpr); in stm32_rtc_wpr_unlock()
192 writel_relaxed(RTC_WPR_2ND_KEY, rtc->base + regs->wpr); in stm32_rtc_wpr_unlock()
197 const struct stm32_rtc_registers *regs = &rtc->data->regs; in stm32_rtc_wpr_lock()
199 writel_relaxed(RTC_WPR_WRONG_KEY, rtc->base + regs->wpr); in stm32_rtc_wpr_lock()
254 struct stm32_rtc_registers regs = rtc->data->regs; in stm32_rtc_pinmux_action_alarm()
255 unsigned int cr = readl_relaxed(rtc->base + regs.cr); in stm32_rtc_pinmux_action_alarm()
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/linux/sound/soc/sti/
H A Duniperif_player.c1 // SPDX-License-Identifier: GPL-2.0-only
17 * Some hardware-related definitions
27 #define UNIPERIF_PLAYER_CLK_ADJ_MIN -999999
61 static irqreturn_t uni_player_irq_handler(int irq, void *dev_id) in uni_player_irq_handler() argument
68 spin_lock(&player->irq_lock); in uni_player_irq_handler()
69 if (!player->substream) in uni_player_irq_handler()
72 snd_pcm_stream_lock(player->substream); in uni_player_irq_handler()
73 if (player->state == UNIPERIF_STATE_STOPPED) in uni_player_irq_handler()
82 dev_err(player->dev, "FIFO underflow error detected\n"); in uni_player_irq_handler()
85 if (player->underflow_enabled) { in uni_player_irq_handler()
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/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8365.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 #include <dt-bindings/clock/mediatek,mt8365-clk.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/memory/mediatek,mt8365-larb-port.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/power/mediatek,mt8365-power.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
21 #size-cells = <2>;
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H A Dmt2712e.dtsi5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt2712-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/memory/mt2712-larb-port.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt2712-power.h>
14 #include "mt2712-pinfunc.h"
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
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H A Dmt8173.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/mt8173-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/memory/mt8173-larb-port.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/power/mt8173-power.h>
13 #include <dt-bindings/reset/mt8173-resets.h>
14 #include <dt-bindings/gce/mt8173-gce.h>
15 #include <dt-bindings/thermal/thermal.h>
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