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/linux/Documentation/devicetree/bindings/serial/
H A Dnxp,sc16is7xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP SC16IS7xx Advanced Universal Asynchronous Receiver-Transmitter (UART)
10 - Hugo Villeneuve <hvilleneuve@dimonoff.com>
15 - nxp,sc16is740
16 - nxp,sc16is741
17 - nxp,sc16is750
18 - nxp,sc16is752
19 - nxp,sc16is760
[all …]
/linux/drivers/tty/serial/
H A Dpmac_zilog.c1 // SPDX-License-Identifier: GPL-2.0+
17 * 2004-08-06 Harald Welte <laforge@gnumonks.org>
18 * - Enable BREAK interrupt
19 * - Add support for sysreq
21 * TODO: - Add DMA support
22 * - Defer port shutdown to a few seconds after close
23 * - maybe put something right into uap->clk_divisor
67 MODULE_DESCRIPTION("Driver for the Mac and PowerMac serial ports.");
80 #define pmz_debug(fmt, arg...) pr_debug("ttyPZ%d: " fmt, uap->port.line, ## arg)
81 #define pmz_error(fmt, arg...) pr_err("ttyPZ%d: " fmt, uap->port.line, ## arg)
[all …]
H A Dsc16is7xx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * SC16IS7xx tty serial driver - common code
53 * - only on 75x/76x
56 * - only on 75x/76x
59 * - only on 75x/76x
62 * - only on 75x/76x
90 /* IER register bits - write only if (EFR[4] == 1) */
91 #define SC16IS7XX_IER_SLEEP_BIT BIT(4) /* Enable Sleep mode */
103 /* FCR register bits - write only if (EFR[4] == 1) */
113 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
[all …]
H A Dpmac_zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * At most 2 ESCCs with 2 ports each
25 * of "escc" node (ie. ch-a or ch-b)
32 /* Port type as obtained from device tree (IRDA, modem, ...) */
64 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
66 return uap->mate; in pmz_get_port_A()
78 writeb(reg, port->control_reg); in read_zsreg()
79 return readb(port->control_reg); in read_zsreg()
85 writeb(reg, port->control_reg); in write_zsreg()
86 writeb(value, port->control_reg); in write_zsreg()
[all …]
H A Dvt8500_serial.c1 // SPDX-License-Identifier: GPL-2.0
35 #define VT8500_URICR 0x0010 /* IrDA control */
74 #define VT8500_CS8 (1 << 2) /* 8-bit data length (vs. 7-bit) */
80 #define VT8500_DMA (1 << 8) /* Enable DMA mode (needs FIFO) */
83 #define VT8500_SWRTSCTS (1 << 11) /* Software-controlled RTS/CTS */
86 * Capability flags (driver-internal)
105 * we use this variable to keep track of which ports
106 * have been allocated as we can't use pdev->id in
114 writel(val, port->membase + off); in vt8500_write()
119 return readl(port->membase + off); in vt8500_read()
[all …]
H A Dsh-sci.c1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 * Copyright (C) 2002 - 2011 Paul Mundt
9 * based off of the old drivers/char/sh-sci.c by:
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
26 #include <linux/dma-mapping.h>
58 #include "sh-sci.h"
60 /* Offsets into the sci_port->irqs array */
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
[all …]
/linux/drivers/usb/serial/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
11 ports, or acts like a serial device, and you want to connect it to
14 Please read <file:Documentation/usb/usb-serial.rst> for more
30 allows logins in single user mode). This could be useful if some
50 read <file:Documentation/usb/usb-serial.rst> for more information on
61 - Suunto ANT+ USB device.
62 - Medtronic CareLink USB device
63 - Fundamental Software dongle.
64 - Google USB serial devices
65 - HP4x calculators
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/linux/Documentation/arch/arm/sa1100/
H A Dassabet.rst2 The Intel Assabet (SA-1110 evaluation) board
13 -------------------
25 -----------------------
39 John Dorsey has produced add-on patches to add support for Assabet and
55 - ftp://ftp.netwinder.org/users/n/nico/
56 - ftp://ftp.arm.linux.org.uk/pub/linux/arm/people/nico/
57 - ftp://ftp.handhelds.org/pub/linux/arm/sa-1100-patches/
59 Look for redboot-assabet*.tgz. Some installation infos are provided in
60 redboot-assabet*.txt.
64 -----------------------------
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/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi3660-hikey960.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
12 #include "hikey960-pinctrl.dtsi"
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/usb/pd.h>
20 compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
35 stdout-path = "serial6:115200n8";
44 reserved-memory {
[all …]
/linux/include/linux/amba/
H A Dserial.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/include/asm-arm/hardware/serial_amba.h
5 * Internal header file for AMBA serial ports
20 /* -------------------------------------------------------------------------------
22 * -------------------------------------------------------------------------------
38 #define UART01x_ILPR 0x20 /* IrDA low power counter register. */
122 #define UART01x_CR_IIRLP BIT(2) /* SIR low power mode */
/linux/drivers/tty/serial/8250/
H A D8250.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Driver for 8250/16550-type serial ports
79 #define UART_CAP_AFE BIT(11) /* MCR-based hw flow control */
84 #define UART_CAP_IRDA BIT(16) /* UART supports IrDA line discipline */
137 return up->port.serial_in(&up->port, offset); in serial_in()
142 up->port.serial_out(&up->port, offset, value); in serial_out()
146 * serial_lsr_in - Read LSR register and preserve flags across reads
149 * Read LSR register and handle saving non-preserved flags across reads.
151 * up->lsr_saved_flags.
157 u16 lsr = up->lsr_saved_flags; in serial_lsr_in()
[all …]
H A D8250_exar.c1 // SPDX-License-Identifier: GPL-2.0
3 * Probe module for 8250/16550-type Exar chips PCI serial ports.
101 #define UART_EXAR_SLEEP 0x8b /* Sleep mode */
105 #define UART_FCTR_EXAR_IRDA 0x10 /* IrDa data encode select */
112 #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
113 #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
131 #define UART_EXAR_DLD_485_POLARITY 0x80 /* RS-485 Enable Signal Polarity */
148 * ---- ---- --------
149 * 0 2 Mode bit 0
150 * 1 2 Mode bit 1
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/linux/arch/m68k/include/asm/
H A DMC68EZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
27 * 0xFFFFF0xx -- System Control
37 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
40 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
43 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
53 * 0xFFFFF1xx -- Chip-Select logic
84 #define CSA_EN 0x0001 /* Chip-Select Enable */
85 #define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
[all …]
H A DMC68VZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers
5 * Copyright (c) 2000-2001 Lineo Inc. <www.lineo.com>
6 * Copyright (c) 2000-2001 Lineo Canada Corp. <www.lineo.ca>
9 * Based on include/asm-m68knommu/MC68332.h
29 * 0xFFFFF0xx -- System Control
39 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
42 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
45 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
55 * 0xFFFFF1xx -- Chip-Select logic
[all …]
H A DMC68328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68328.h: '328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
26 * 0xFFFFF0xx -- System Control
36 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
39 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
42 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
52 * 0xFFFFF1xx -- Chip-Select logic
58 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
76 #define GRPBASE_GBA_MASK 0xfff0 /* Group Base Address (bits 31-20) */
[all …]
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124-venice2.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
18 stdout-path = "serial0:115200n8";
29 vdd-supply = <&vdd_3v3_hdmi>;
30 pll-supply = <&vdd_hdmi_pll>;
31 hdmi-supply = <&vdd_5v0_hdmi>;
33 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
34 nvidia,hpd-gpio =
41 avdd-io-hdmi-dp-supply = <&vdd_1v05_run>;
[all …]
H A Dtegra20-asus-tf101.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/atmel-maxtouch.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra20-cpu-opp.dtsi"
11 #include "tegra20-cpu-opp-microvolt.dtsi"
16 chassis-type = "convertible";
33 * pre-existing /chosen node to be available to insert the
[all …]
H A Dtegra124-jetson-tk1.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
7 #include "tegra124-jetson-tk1-emc.dtsi"
11 compatible = "nvidia,jetson-tk1", "nvidia,tegra124";
17 /* This order keeps the mapping DB9 connector <-> ttyS0 */
24 stdout-path = "serial0:115200n8";
34 avddio-pex-supply = <&vdd_1v05_run>;
35 dvddio-pex-supply = <&vdd_1v05_run>;
36 avdd-pex-pll-supply = <&vdd_1v05_run>;
[all …]
H A Dtegra124-apalis-v1.2.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2016-2018 Toradex AG
7 #include "tegra124-apalis-emc.dtsi"
21 avddio-pex-supply = <&reg_1v05_vdd>;
22 avdd-pex-pll-supply = <&reg_1v05_vdd>;
23 avdd-pll-erefe-supply = <&reg_1v05_avdd>;
24 dvddio-pex-supply = <&reg_1v05_vdd>;
25 hvdd-pex-pll-e-supply = <&reg_module_3v3>;
26 hvdd-pex-supply = <&reg_module_3v3>;
27 vddio-pex-ctl-supply = <&reg_module_3v3>;
[all …]
H A Dtegra124-apalis.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright 2016-2019 Toradex AG
7 #include "tegra124-apalis-emc.dtsi"
20 avddio-pex-supply = <&reg_1v05_vdd>;
21 avdd-pex-pll-supply = <&reg_1v05_vdd>;
22 avdd-pll-erefe-supply = <&reg_1v05_avdd>;
23 dvddio-pex-supply = <&reg_1v05_vdd>;
24 hvdd-pex-pll-e-supply = <&reg_module_3v3>;
25 hvdd-pex-supply = <&reg_module_3v3>;
26 vddio-pex-ctl-supply = <&reg_module_3v3>;
[all …]
/linux/arch/arm/mach-footbridge/
H A Dnetwinder-hw.c1 // SPDX-License-Identifier: GPL-2.0
3 * linux/arch/arm/mach-footbridge/netwinder-hw.c
20 #include <asm/mach-types.h>
65 * This is a lock for accessing ports GP1_IO_BASE and GP2_IO_BASE
177 * mode 1 == EPP in wb977_init_printer()
219 * Initialise the Winbond W83977F Infra-Red device
231 * IRDA IRQ 6, active high, edge trigger in wb977_init_irda()
237 * RX DMA - ISA DMA 0 in wb977_init_irda()
242 * TX DMA - Disable Tx DMA in wb977_init_irda()
267 current_gpio_io = -1; in wb977_init_gpio()
[all …]
/linux/Documentation/admin-guide/
H A Ddevices.txt1 0 Unnamed devices (e.g. non-device mounts)
7 2 = /dev/kmem OBSOLETE - replaced by /proc/kcore
11 6 = /dev/core OBSOLETE - replaced by /proc/kcore
18 12 = /dev/oldmem OBSOLETE - replaced by /proc/vmcore
31 2 char Pseudo-TTY masters
37 Pseudo-tty's are named as follows:
40 the 1st through 16th series of 16 pseudo-ttys each, and
44 These are the old-style (BSD) PTY devices; Unix98
106 3 char Pseudo-TTY slaves
112 These are the old-style (BSD) PTY devices; Unix98
[all …]
/linux/arch/powerpc/platforms/powermac/
H A Dfeature.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 1996-2001 Paul Mackerras (paulus@cs.anu.edu.au)
8 * - Replace mdelay with some schedule loop if possible
9 * - Shorten some obfuscated delays on some routines (like modem
11 * - Refcount some clocks (see darwin)
12 * - Split split split...
37 #include <asm/pci-bridge.h>
81 child = child->parent; in macio_find()
147 return -ENODEV; in simple_feature_tweak()
171 return -ENODEV; in ohare_htw_scc_enable()
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/linux/arch/alpha/kernel/
H A Dsmc37c669.c60 * er 28-Jan-1997 Initial Entry
69 ** The mask acts as a flag used in mapping actual ISA IRQs (0 - 15)
70 ** to device IRQs (A - H).
84 ** channels to device DMA channels (A - C).
209 ** The INDEX (write only) and DATA (read/write) ports are effective
218 ** CR00 - default value 0x28
221 ** 0x - 30ua pull-ups on nIDEEN, nHDCS0, NHDCS1
222 ** 11 - IRQ_H available as IRQ output,
224 ** 10 - nIDEEN, nHDCS0, nHDCS1 used to control IDE
247 ** CR01 - default value 0x9C
[all …]
/linux/arch/mips/include/asm/mach-au1x00/
H A Dau1000.h6 * Copyright 2000-2001, 2006-2008 MontaVista Software Inc.
38 /* Au1000-style (IC0/1): 2 controllers with 32 sources each */
45 /* Au1300-style (GPIC): 1 controller with up to 128 sources */
48 #define ALCHEMY_GPIC_INT_LAST (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1)
507 /* Don't allow any legacy ports probing */
537 #define PCI_CONFIG_ET (1 << 26) /* error in target mode */
544 #define PCI_CONFIG_NC (1 << 16) /* mark mem access non-coherent */
545 #define PCI_CONFIG_IA (1 << 15) /* INTA# enabled (target mode) */
559 #define PCI_CONFIG_R2H (1 << 2) /* REQ2# to hi-prio arbiter */
560 #define PCI_CONFIG_R1H (1 << 1) /* REQ1# to hi-prio arbiter */
[all …]

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