Lines Matching +full:irda +full:- +full:mode +full:- +full:ports
6 * Copyright 2000-2001, 2006-2008 MontaVista Software Inc.
38 /* Au1000-style (IC0/1): 2 controllers with 32 sources each */
45 /* Au1300-style (GPIC): 1 controller with up to 128 sources */
48 #define ALCHEMY_GPIC_INT_LAST (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1)
507 /* Don't allow any legacy ports probing */
537 #define PCI_CONFIG_ET (1 << 26) /* error in target mode */
544 #define PCI_CONFIG_NC (1 << 16) /* mark mem access non-coherent */
545 #define PCI_CONFIG_IA (1 << 15) /* INTA# enabled (target mode) */
559 #define PCI_CONFIG_R2H (1 << 2) /* REQ2# to hi-prio arbiter */
560 #define PCI_CONFIG_R1H (1 << 1) /* REQ1# to hi-prio arbiter */
561 #define PCI_CONFIG_CH (1 << 0) /* PCI ctl to hi-prio arbiter */
635 /* Early Au1000 have a write-only SYS_CPUPLL register. */
652 * early revisions of Alchemy SOCs. It disables the bus trans- in au1xxx_cpu_needs_config_od()
674 #define ALCHEMY_CPU_UNKNOWN -1
761 for (i = 10000; i; i--) in alchemy_uart_putchar()
763 } while (--timeout); in alchemy_uart_putchar()
808 /* The IrDA peripheral has an IRFIRSEL pin, but on the DB/PB boards it's
809 * not used to select FIR/SIR mode on the transceiver but as a GPIO.
810 * Instead a CPLD has to be told about the mode. The driver calls the
818 void (*set_phy_mode)(int mode);
823 * GPIO controller or a on-chip peripheral.
828 /* wake-from-str pins 0-3 */
831 /* external clock sources for PSCs: 4-5 */
833 /* 8bit MMC interface on SD0: 6-9 */
838 /* UART1 pins: 11-18 */
842 /* UART0 pins: 19-24 */
845 /* UART2: 25-26 */
847 /* UART3: 27-28 */
849 /* LCD controller PWMs, ext pixclock: 29-31 */
851 /* SD1 interface: 32-37 */
854 /* SD2 interface: 38-43 */
857 /* PSC0/1 clocks: 44-45 */
859 /* PSCs: 46-49/50-53/54-57/58-61 */
868 /* PCMCIA interface: 62-70 */
872 /* camera interface H/V sync inputs: 71-72 */
874 /* PSC2/3 clocks: 73-74 */