Searched +full:ipq9574 +full:- +full:ppe (Results 1 – 2 of 2) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ957410 - Bjorn Andersson <andersson@kernel.org>11 - Anusha Rao <quic_anusha@quicinc.com>15 resets on IPQ957418 include/dt-bindings/clock/qcom,ipq9574-nsscc.h19 include/dt-bindings/reset/qcom,ipq9574-nsscc.h[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.7 * CMN PLL block expects the reference clock from on-board Wi-Fi block,9 * blocks and to GCC. The networking related blocks include PPE (packet13 * On the IPQ9574 SoC, there are three clocks with 50 MHZ and one clock15 * and one clock with 353 MHZ to PPE. The other fixed rate output clocks19 * On the IPQ5424 SoC, there is an output clock from CMN PLL to PPE at 375 MHZ,21 * clocks from CMN PLL on IPQ5424 are the same as IPQ9574.23 * +---------+25 * +--+---+--+[all …]