/linux/drivers/mailbox/ |
H A D | stm32-ipcc.c | 54 spinlock_t lock; /* protect access to IPCC registers */ 84 struct stm32_ipcc *ipcc = data; in stm32_ipcc_rx_irq() local 85 struct device *dev = ipcc->controller.dev; in stm32_ipcc_rx_irq() 91 proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST; in stm32_ipcc_rx_irq() 92 tosr = readl_relaxed(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); in stm32_ipcc_rx_irq() 93 mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR); in stm32_ipcc_rx_irq() 98 for (chan = 0; chan < ipcc->n_chans; chan++) { in stm32_ipcc_rx_irq() 104 mbox_chan_received_data(&ipcc->controller.chans[chan], NULL); in stm32_ipcc_rx_irq() 106 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR, in stm32_ipcc_rx_irq() 117 struct stm32_ipcc *ipcc = data; in stm32_ipcc_tx_irq() local [all …]
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/linux/Documentation/devicetree/bindings/mailbox/ |
H A D | qcom-ipcc.yaml | 4 $id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml# 13 The Inter-Processor Communication Controller (IPCC) is a centralized hardware 20 protocol (protocol-id is 0). Refer include/dt-bindings/mailbox/qcom-ipcc.h 27 - qcom,qcs8300-ipcc 28 - qcom,qdu1000-ipcc 29 - qcom,sa8255p-ipcc 30 - qcom,sa8775p-ipcc 31 - qcom,sar2130p-ipcc 32 - qcom,sc7280-ipcc 33 - qcom,sc8280xp-ipcc [all …]
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H A D | st,stm32-ipcc.yaml | 4 $id: http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml# 10 The IPCC block provides a non blocking signaling mechanism to post and 21 const: st,stm32mp1-ipcc 64 ipcc: mailbox@4c001000 { 65 compatible = "st,stm32mp1-ipcc"; 72 clocks = <&rcc_clk IPCC>;
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/linux/sound/soc/intel/catpt/ |
H A D | ipc.c | 64 catpt_writel_shim(cdev, IPCC, header); in catpt_dsp_send_tx() 268 u32 isc, ipcc; in catpt_dsp_irq_handler() local 278 ipcc = catpt_readl_shim(cdev, IPCC); in catpt_dsp_irq_handler() 279 trace_catpt_ipc_reply(ipcc); in catpt_dsp_irq_handler() 280 catpt_dsp_copy_rx(cdev, ipcc); in catpt_dsp_irq_handler() 284 catpt_updatel_shim(cdev, IPCC, CATPT_IPCC_DONE, 0); in catpt_dsp_irq_handler()
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H A D | dsp.c | 334 catpt_writel_shim(cdev, IPCC, CATPT_IPCC_DEFAULT); in catpt_dsp_set_regs_defaults()
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/linux/arch/arm/boot/dts/st/ |
H A D | stm32mp15xx-osd32.dtsi | 200 &ipcc { 207 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
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H A D | stm32mp157a-microgea-stm32mp1.dtsi | 116 &ipcc { 128 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
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H A D | stm32mp15xx-dhcor-som.dtsi | 218 &ipcc { 230 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
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H A D | stm32mp157c-odyssey-som.dtsi | 221 &ipcc { 233 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
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H A D | stm32mp157a-icore-stm32mp1.dtsi | 164 &ipcc { 176 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
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H A D | stm32mp157c-ed1.dts | 317 &ipcc { 329 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
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H A D | stm32mp157c-emstamp-argon.dtsi | 358 &ipcc { 370 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
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H A D | stm32mp157c-phycore-stm32mp15-som.dtsi | 389 &ipcc { 408 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
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/linux/Documentation/devicetree/bindings/remoteproc/ |
H A D | qcom,glink-edge.yaml | 81 #include <dt-bindings/mailbox/qcom-ipcc.h> 88 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 91 mboxes = <&ipcc IPCC_CLIENT_WPSS
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H A D | qcom,sm6375-pas.yaml | 106 #include <dt-bindings/mailbox/qcom-ipcc.h> 134 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 137 mboxes = <&ipcc IPCC_CLIENT_LPASS
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H A D | qcom,sc8280xp-pas.yaml | 105 #include <dt-bindings/mailbox/qcom-ipcc.h> 137 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 140 mboxes = <&ipcc IPCC_CLIENT_LPASS
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H A D | qcom,sm6350-pas.yaml | 128 #include <dt-bindings/mailbox/qcom-ipcc.h> 157 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 160 mboxes = <&ipcc IPCC_CLIENT_LPASS
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H A D | qcom,sc7280-adsp-pil.yaml | 149 #include <dt-bindings/mailbox/qcom-ipcc.h> 186 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 189 mboxes = <&ipcc IPCC_CLIENT_LPASS
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H A D | qcom,sc7280-mss-pil.yaml | 209 #include <dt-bindings/mailbox/qcom-ipcc.h> 260 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 263 mboxes = <&ipcc IPCC_CLIENT_MPSS
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/linux/Documentation/devicetree/bindings/misc/ |
H A D | qcom,fastrpc.yaml | 110 #include <dt-bindings/mailbox/qcom-ipcc.h> 113 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 116 mboxes = <&ipcc IPCC_CLIENT_LPASS
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/linux/arch/arm64/boot/dts/qcom/ |
H A D | sa8775p.dtsi | 15 #include <dt-bindings/mailbox/qcom-ipcc.h> 723 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 726 mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P>; 746 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 749 mboxes = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; 769 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 772 mboxes = <&ipcc IPCC_CLIENT_NSP1 IPCC_MPROC_SIGNAL_SMP2P>; 792 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 795 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 IPCC_MPROC_SIGNAL_SMP2P>; 815 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1 [all …]
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H A D | x1e80100.dtsi | 16 #include <dt-bindings/mailbox/qcom-ipcc.h> 723 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 727 mboxes = <&ipcc IPCC_CLIENT_LPASS 749 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 753 mboxes = <&ipcc IPCC_CLIENT_CDSP 801 ipcc: mailbox@408000 { label 802 compatible = "qcom,x1e80100-ipcc", "qcom,ipcc"; 3975 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3978 mboxes = <&ipcc IPCC_CLIENT_LPASS 5649 interrupt-parent = <&ipcc>; [all …]
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/linux/include/dt-bindings/clock/ |
H A D | stm32mp1-clks.h | 96 #define IPCC 83 macro
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/linux/sound/soc/sof/intel/ |
H A D | shim.h | 99 /* IPCX / IPCC */
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/linux/drivers/clk/stm32/ |
H A D | clk-stm32mp1.c | 1966 PCLK(IPCC, "ipcc", "ck_mcu", 0, G_IPCC),
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