| /linux/Documentation/devicetree/bindings/iommu/ |
| H A D | iommu.txt | 5 IOMMU device node:
8 An IOMMU can provide the following services:
13 Example: 32-bit DMA to 64-bit physical addresses
15 * Implement scatter-gather at page level granularity so that the device does
19 through the IOMMU and faulting when encountering accesses to unmapped
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
30 typically have a fixed association to the master device, whereas multiple-
31 master IOMMU devices can translate accesses from more than one master.
33 The device tree node of the IOMMU device's parent bus must contain a valid
34 "dma-ranges" property that describes how the physical address space of the
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| H A D | ti,omap-iommu.txt | 1 OMAP2+ IOMMU
4 - compatible : Should be one of,
5 "ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances
6 "ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances
7 "ti,dra7-dsp-iommu" for DRA7xx DSP IOMMU instances
8 "ti,dra7-iommu" for DRA7xx IOMMU instances
9 - ti,hwmods : Name of the hwmod associated with the IOMMU instance
10 - reg : Address space for the configuration registers
11 - interrupts : Interrupt specifier for the IOMMU instance
12 - #iommu-cells : Should be 0. OMAP IOMMUs are all "single-master" devices,
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| H A D | qcom,apq8064-iommu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $id: http://devicetree.org/schemas/iommu/qcom,apq8064-iommu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Qualcomm APQ8064 IOMMU
11 - David Heidelberg <david@ixit.cz>
14 The MSM IOMMU is an implementation compatible with the ARM VMSA short
16 outside of the CPU, each connected to the IOMMU through a port called micro-TLB.
20 const: qcom,apq8064-iommu
24 - description: interface clock for register accesses
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| /linux/Documentation/devicetree/bindings/misc/ |
| H A D | fsl,qoriq-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/fsl,qoriq-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 The Freescale Management Complex (fsl-mc) is a hardware resource
15 network-oriented packet processing applications. After the fsl-mc
22 For an overview of the DPAA2 architecture and fsl-mc bus see:
26 same hardware "isolation context" and a 10-bit value called an ICID
31 between ICIDs and IOMMUs, so an iommu-map property is used to define
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | pci-iommu.txt | 2 relationship between PCI(e) devices and IOMMU(s).
17 Requester ID. While a given PCI device can only master through one IOMMU, a
18 root complex may split masters across a set of IOMMUs (e.g. with one IOMMU per
22 and a mechanism is required to map from a PCI device to its IOMMU and sideband
25 For generic IOMMU bindings, see
26 Documentation/devicetree/bindings/iommu/iommu.txt.
33 -------------------
35 - iommu-map: Maps a Requester ID to an IOMMU and associated IOMMU specifier
39 (rid-base,iommu,iommu-base,length).
41 Any RID r in the interval [rid-base, rid-base + length) is associated with
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| /linux/Documentation/devicetree/bindings/media/ |
| H A D | ti,omap3isp.txt | 4 The DT definitions can be found in include/dt-bindings/media/omap3-isp.h.
9 compatible : must contain "ti,omap3-isp"
15 interrupts : the ISP interrupt specifier
16 iommus : phandle and IOMMU specifier for the IOMMU that serves the ISP
17 syscon : the phandle and register offset to the Complex I/O or CSI-PHY
19 ti,phy-type : 0 -- OMAP3ISP_PHY_TYPE_COMPLEX_IO (e.g. 3430)
20 1 -- OMAP3ISP_PHY_TYPE_CSIPHY (e.g. 3630)
21 #clock-cells : Must be 1 --- the ISP provides two external clocks,
24 clock bindings in ../clock/clock-bindings.txt.
27 ---------------------
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| H A D | samsung,fimc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
14 The S5P/Exynos SoC Camera subsystem comprises of multiple sub-devices
17 CSIS, FIMC-LITE and FIMC-IS (ISP).
25 '#address-cells':
28 '#size-cells':
31 '#clock-cells':
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| /linux/Documentation/devicetree/bindings/display/mediatek/ |
| H A D | mediatek,wdma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
24 - enum:
25 - mediatek,mt8173-disp-wdma
26 - items:
27 - const: mediatek,mt6795-disp-wdma
28 - const: mediatek,mt8173-disp-wdma
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| /linux/Documentation/devicetree/bindings/powerpc/fsl/ |
| H A D | srio-rmu.txt | 5 node is composed of three types of sub-nodes ("fsl-srio-msg-unit",
6 "fsl-srio-dbell-unit" and "fsl-srio-port-write-unit").
10 - compatible
13 Definition: Must include "fsl,srio-rmu-vX.Y", "fsl,srio-rmu".
18 - reg
20 Value type: <prop-encoded-array>
25 - fsl,liodn
26 Usage: optional-but-recommended (for devices with PAMU)
27 Value type: <prop-encoded-array>
28 Definition: The logical I/O device number for the PAMU (IOMMU) to be
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| H A D | srio.txt | 5 - compatible
11 Optionally, a compatible string of "fsl,srio-vX.Y" where X is Major
15 - reg
17 Value type: <prop-encoded-array>
22 - interrupts
24 Value type: <prop_encoded-array>
27 specifier. The format of the specifier is defined by the
31 property. (Typically shared with port-write).
33 - fsl,srio-rmu-handle:
37 (See srio-rmu.txt for more details on RMU node binding)
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| /linux/Documentation/devicetree/bindings/remoteproc/ |
| H A D | ti,omap-remoteproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
17 The processor cores in the sub-system are usually behind an IOMMU, and may
18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
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| /linux/Documentation/core-api/ |
| H A D | dma-api-howto.rst | 10 with example pseudo-code. For a concise description of the API, see
11 Documentation/core-api/dma-api.rst.
39 supports 64-bit addresses for main memory and PCI BARs, it may use an IOMMU
40 so devices only need to use 32-bit DMA addresses.
49 +-------+ +------+ +------+
52 C +-------+ --------> B +------+ ----------> +------+ A
54 +-----+ | | | | bridge | | +--------+
55 | | | | +------+ | | | |
58 +-----+ +-------+ +------+ +------+ +--------+
60 X +-------+ --------> Y +------+ <---------- +------+ Z
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| /linux/Documentation/admin-guide/ |
| H A D | kernel-parameters.txt | 16 force -- enable ACPI if default was off
17 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
18 off -- disable ACPI if default was on
19 noirq -- do not use ACPI for IRQ routing
20 strict -- Be less tolerant of platforms that are not
22 rsdt -- prefer RSDT over (default) XSDT
23 copy_dsdt -- copy DSDT to memory
24 nospcr -- disable console in ACPI SPCR table as
41 If set to vendor, prefer vendor-specific driver
73 Documentation/firmware-guide/acpi/debug.rst for more information about
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| /linux/drivers/of/ |
| H A D | base.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 1996-2005 Paul Mackerras.
67 node_name = kbasename(np->full_name); in of_node_name_eq()
68 len = strchrnul(node_name, '@') - node_name; in of_node_name_eq()
79 return strncmp(kbasename(np->full_name), prefix, strlen(prefix)) == 0; in of_node_name_prefix()
99 for (; np; np = np->parent) { in of_bus_n_addr_cells()
100 if (!of_property_read_u32(np, "#address-cells", &cells)) in of_bus_n_addr_cells()
103 * Default root value and walking parent nodes for "#address-cells" in of_bus_n_addr_cells()
108 "Missing '#address-cells' in %pOF\n", np); in of_bus_n_addr_cells()
115 if (np->parent) in of_n_addr_cells()
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| /linux/include/linux/ |
| H A D | pci.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
60 * The PCI interface treats multi-function devices as independent
68 * In the interest of not exposing interfaces to user-space unnecessarily,
69 * the following kernel-only defines are being added here.
80 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
86 return kobject_name(&slot->kob in pci_slot_name()
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| /linux/include/uapi/drm/ |
| H A D | drm_fourcc.h | 39 * further describe the buffer's format - for example tiling or compression.
42 * ----------------
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
58 * may preserve meaning - such as number of planes - from the fourcc code,
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
76 * - Kernel and user-space drivers: for drivers it's important that modifiers
80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
93 * -----------------------
98 * upstream in-kernel or open source userspace user does not apply.
110 /* Reserve 0 for the invalid format specifier */
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| /linux/drivers/pci/controller/ |
| H A D | pci-hyperv.c | 1 // SPDX-License-Identifier: GPL-2.0
8 * This driver acts as a paravirtual front-end for PCI Express root buses.
9 * When a PCI Express function (either an entire device or an SR-IOV
13 * VM within Hyper-V, there may seem to be no PCI bus at all in the VM
18 * to the VM using this front-end will appear at "device 0", the domain will
24 * MSI or MSI-X) associated with the functions on the bus. As interrupts are
28 * vector. This driver does not support level-triggered (line-based)
32 * The rest of this driver mostly maps PCI concepts onto underlying Hyper-V
34 * by Hyper-V is mapped into a single page of memory space, and the
37 * the PCI back-end driver in Hyper-V.
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